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MIPI D-PHY Simulation Verification IP (VIP)

Specification Support

Our MIPI D-PHY Simulation VIP supports the latest MIPI D-PHY specifications.

Product Highlights

  • Industry's first D-PHY VIP
  • Part of the broadest line of MIPI simulation VIP 
  • Cadence has been a MIPI Alliance Contributing Member since 2007
  • Supports one to four data lanes
  • Supports Ultra-Low Power mode (ULPM)

Key Features

Feature Name

Description

Phy interfaces

 

Supports both PHY interfaces (DpDn and PPI)

Physical layer

Includes the MIPI D-PHY VIP for physical layer verification

Data lanes

Supports one to four data lanes

Interleaving

Supports virtual channel and data type interleaving

Ultra-Low Power mode (ULPM)

Supports Ultra-Low Power mode (ULPM)

Trigger

Supports trigger commands, including low-power data after trigger

Memory callbacks for DPHY event notifications

Supports D-PHY (DPDN+PPI) event notifications for scoreboarding

Error injection

Supports injection of errors in the DPHY layers

Data from a file (for e users only)

Supports driving frames from a user data file

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments