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VIP for MIPI CSI-2 v3( includes D-PHY and C-PHY)

Cadence provides a mature and comprehensive Verification IP (VIP) for the CSI-2sm v3 protocol, which is part of the MIPI® family. Incorporating the latest protocol updates, the Cadence® VIP for CSI-2 v3 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CSI-2 v3 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The DSI-2 VIP supports the following MIPI specifications:

Protocol Features

The following table shows key features from the spec that are implemented in the VIP.

Feature Name
Description

Clock

Supports continuous and non-continuous TxWordClkHS and RxWordClkHS clock operation

PPI Data Bus Width

Supports 16- and 32-bit PPI data bus width over C-PHYsm

Supports 8-, 16- and 32-bit PPI data bus width over D-PHYsm

Data Types

YUV → YUV420 8-bit, YUV420 10-bit, Legacy YUV420 8-bit, YUV420 8-bit CSPS, YUV420 10-bit CSPS

RGB → RGB444, RGB555, RGB565, RGB666, RGB888

RAW → RAW6, RAW7, RAW8, RAW10, RAW12, RAW14, RAW16, RAW20, RAW24

Generic Long Packet Data Types 1 to 4, user-defined format 1 to 8, Blanking Data, Null Packet, and Embedded Data

FS-FE, LS-LE, and all Generic Short Packet Codes (1 to 8)

Virtual Channel Extension

Supports up to 32 virtual channels over C-PHY and 16 virtual channels over D-PHY

Receiver and Transmitter Verification

Verifies both CSI-2 receiver and transmitter

PHY Interfaces

Supports D-PHY2-5 and C-PHY2-0 with both PHY interfaces (DpDn and PPI)

Physical Layer

Includes the VIP for MIPI D-PHY and VIP for MIPI C-PHY for physical layer verification

Data Lanes

Supports one to eight PHY data lanes

Interleaving

Supports virtual channel and data type interleaving

Ultra-Low Power Mode (ULPM)

Supports Ultra-Low-Power mode (ULPM) on clock and data lanes

Triggers

Supports all 4 trigger commands, including low-power data after trigger transmission and low-power data pause

Memory Callbacks for PHY Event Notifications

Supports D-PHY and C-PHY (DpDn and PPI) event notifications for scoreboarding

Error Injection

Supports injection of errors in the CSI-2, D-PHY, and C-PHY layers

Pixel Layer

Supports pixel layer for RGB, RAW, and YUV422 data types

Supports pixel-to-byte packing

Scrambling

Supports lane-based data payload scrambling

Supports LFSR initialization for both D-PHY and C-PHY

Supports multiple sync word types insertion for C-PHY scrambling LFSR initialization

Latency Reduction Transport Efficiency (LRTE)

Supports merging multiple packets from the same frame in a single HS burst with protocol generated and consumed fillers and spacers over C-PHY and D-PHY

Efficient Packet Delimiter (EPD)

Supports PHY-generated and -consumed PDQ for both C-PHY and D-PHY

PDQ for D-PHY is HS-IDLE, and for C-PHY is sync words, when merging multiple packets with LRTE

Alternate Calibration Sequence for D-PHY

Supports PRBS9 generation of D-PHY Alternate Calibration Sequence includes updates of D-PHY 2.1 errata01

Frame Synchronization Packets

Supports increment of frame number by 1 or 2 for every FS Packet

Spacer Byte Generation

Supports to redefine spacers as a minimum value, as defined in the CSI2 v2.1 specification

CSI-2 Over CPHY ALP Mode

Supports transmission of High-Speed data bursts as well as control commands

End of Transmission packet (EoTp)

Supports a short packet after the last packet to indicate end of HS burst transmission

Spacers Generation

Supports spacers in the packet without PDQ(Packet Delimiter Quick) for CPHY and DPHY EPD option 1 and variable-length spacers for DPHY EPD option 2

Smart Region of Interest

Supports SEDP Packet and SROI packet option 1 and 2

Unified Serial Link

Supports SNS- and APP-initiated USL transactions in HS/LPDT mode and transport integrity checks
Supports USL BTA switch registers
Supports switching to soft standby and streaming mode
Supports Dynamic clock control

CSI-2 Over DPHY 2.5

ALP Mode - Support of Data transmission and all ALP control bursts

Fast Lane BTA - Burst Turn Around in ALP Mode

Clock Lane ULPS in ALP mode

CSI-2 Over CPHY 2.0

Fast Lane BTA - Burst Turn Around in ALP Mode

 

 Key Verification Capabilities

  • Compliance Management System automates protocol compliance verification.

  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

  • Generates constrained-random bus traffic.

  • Provides extensive coverage, verification plan, and test suite.

  • Complies with the Unified Verification Methodology (UVM, OVM).

  • UVM configuration: The user can configure the VIP agent using the UVM config class.

  • Provides predefined error injection.

Other Supported Features

Feature Name
Description

Testbench Language Interfaces

SystemVerilog and e

UVM Methodology

Up to version 1.2

Trace Debug

Yes

Functional Coverage - e

Yes

Functional Coverage - SystemVerilog

Yes

Compliance Management System

Yes

TripleCheck

Yes

 

Features not yet supported:

  • In case of DUT error, some errors are reported twice in the same clock cycle—the user is advised to ignore the redundant error
  • IPixel layer is not supported for YUV420 data types
  • IThe VIP for MIPI CSI-2 does not include the implementation of CCI, which is based on the I2C or MIPI I3C® interface. To implement it, the user must also get the VIP for MIPI I3C

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments