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MIPI CSI-2 v2 Simulation Verification IP (VIP)

Cadence provides a mature and comprehensive Verification IP (VIP) for the CSI-2sm v2 protocol, which is part of the MIPI® family. Incorporating the latest protocol updates, the Cadence® VIP for CSI-2 v2 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CSI-2 v2 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification Support

The VIP for CSI-2 v2 supports the following specifications:

Product Highlights

  • Compliance Management System automates protocol compliance verification

  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate

  • Generates constrained-random bus traffic

  • Provides extensive coverage, verification plan, and test suite

  • Complies with the Unified Verification Methodology (UVM)

  • Provides predefined error injection

Key Features

The following table shows key features from the spec that are implemented in the VIP.

Feature Name
Clock Supports continuous TxWordClkHS and RxWordClkHS clock operation.
PPI data bus width over C-PHYsm Supports 16- and 32-bit PPI data bus width over C-PHYsm.
PPI data bus width over D-PHYsm Supports 8-, 16- and 32-bit PPI data bus width over D-PHYsm.
New RAW data types Supports RAW16 and RAW20 data types.
Virtual channel extension Supports up to 32 virtual channels over C-PHY and 16 virtual channels over D-PHY.
Receiver and transmitter verification Verifies both CSI-2 receiver and transmitter.
PHY interfaces Supports D-PHY2-1 and C-PHY1-2 with both PHY interfaces (DpDn and PPI).
Physical layer Includes the VIP for MIPI D-PHY and VIP for MIPI C-PHY for physical layer verification.
Data lanes Supports one to eight D-PHY data lanes.
Interleaving Supports virtual channel and data type interleaving.
Ultra-Low Power mode (ULPM) Supports Ultra-Low Power mode (ULPM) on clock and data lanes.
Triggers Supports all 4 trigger commands, including low-power data after trigger transmission and low-power data pause.
Memory callbacks for D-PHY event notifications Supports D-PHY and C-PHY (DpDn and PPI) event notifications for scoreboarding.
Error injection Supports injection of errors in the CSI-2, D-PHY, and C-PHY layers.
Pixel layer Supports pixel layer for RGB, RAW, and YUV422 data types. Supports pixel-to-byte packing.
Scrambling Supports lane-based data payload scrambling as per CSI-2 v2.0 specification. Supports LFSR initialization for both D-PHY and C-PHY Supports multiple sync word types insertion for C-PHY scrambling LFSR initialization
Latency Reduction Transport Efficiency (LRTE) Supports merging multiple packets from the same frame in a single HS burst with protocol generated and consumed fillers and spacers over C-PHY and D-PHY.
Efficient Packet Delimiter (EPD) Supports PHY-generated and -consumed PDQ for both C-PHY and D-PHY. PDQ for D-PHY is HS-IDLE, and for C-PHY is sync words, when merging multiple packets with LRTE.
Alternate Calibration Sequence for DPHY
Supports PRBS9 generation of DPHY Alternate Calibration Sequence includes updates of DPHY 2.1 errata01
Frame Synchronization Packets Supports increment of frame number by 1 or 2 for every FS Packet, as defined in the CSI2 v2.1 spec
Spacer Byte generation Supports to redefine spacers as a minimum value, as defined in the CSI2 v2.1 spec
Generic Long Packet data type 1-4 Supports to generate Long Packet data types 1 through 4, as defined in the CSI2 v2.1 spec
CSI-2 Over CPHY ALP Mode Supports transmission of High Speed data bursts as well as control commands, as defined in the CSI2 v2.1 spec


Other Supported Features

Testbench Language Interfaces

SystemVerilog, e 

UVM Methodology

Up to version 1.2

Trace Debug


Functional Coverage - e


Functional Coverage - SV


Compliance Management System





Supported Design-Under-Test Configurations

Transmitter Receiver Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments