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MIPI C-PHY Simulation Verification IP (VIP)

The Cadence® Verification IP (VIP) for MIPI® C-PHYsm provides a mature, highly capable compliance verification solution for the MIPI C-PHY protocol. Incorporating the latest protocol updates, the VIP for C-PHY provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. It includes highly configurable and flexible simulation models of all the protocol layers, devices, and transaction types.

Designed for easy integration in testbenches at the IP, system-on-chip (SoC), and system levels, the VIP for C-PHY helps you reduce time to test, accelerate verification closure, and ensure end-product quality. Our VIP runs on all major simulators (Cadence Incisive® Enterprise Simulator and third-party simulators). The VIP supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM). It supports integration and traffic generation in all popular verification environments.

The VIP for C-PHY is not a standalone product, but can be used as the PHY layer of CSI-2sm, CSI-2 2.0, and DSI-2sm.

Specification Support

Product Highlights

  • First to market with C-PHY VIP support
  • Supports Low and High Speed transactions
  • Supports multi-lane configuration

Key Features

Feature Name
HS transactions Supports transmitting and receiving C-PHY High Speed transactions.
Preamble and Sync Pattern and Post fields Supports all parts of HS transaction (Preamble -> Sync Pattern -> data -> Post pattern)
(Both PreBegin and Post length can be changed at run time).
Sync Word Supports driving and detecting sync words during HS transaction.
LP - HS transitions Supports transitions from LP to HS and vice versa.
Number of lanes Supports 1 to 4 lanes.
C-PHY symbol error injection Supports an API to inject C-PHY symbol errors (wrong symbol/missing symbol).
Prog-seq Supports injection and detection of optional user programmable sequence as part of the HS preamble.
C-PHY PPI Supports CPHY Protocol Phy Interface - data bus of 16 bits, additional txsendsynchs and rxinvalidcodehs signals.
C-PHY checkers for sensor side Supports C-PHY level checkers on the sensor (master DUT).

Key Verification Capabilities

Debug information is embedded at the core and also at the Verilog level to simplify the debug process.

Other Supported Features

Feature Name
Testbench Language Interfaces SystemVerilog and e
Methodology UVM and OVM
Trace Debug Yes
Functional Coverage - e Yes
Functional Coverage - SV Yes
Compliance Management System -
TripleCheck -
Interconnect Validator -
Simulator Support IES, VCS, and MTI

Supported Design-Under-Test Configurations

Transmitter Receiver
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments