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VIP for Ethernet up to 100G

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet up to 100G protocols provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for Ethernet up to 100G helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet up to 100G runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

The VIP for Ethernet up to 100G enables verification of Ethernet interfaces in standalone, partial stack, and full stack mode for speeds from 10Mbps to 100Gbps:

  • XMII level, that is, between MAC and PHY
  • Between PHY sub-layers, that is, PCS, PMA, PMD
  • Between link partners, that is, TX Station and RX Station

The VIP for Ethernet up to 100G complies with IEEE 802.3 Ethernet standards and draft specifications. It supports other widely popular Ethernet interfaces, which are proprietary and based on IEEE 802.3.

 

Specification Support

  • IEEE 802.3-2015
  • IEEE 802.3 by and consortium 25/50G
  • IEEE 802.3cdD3p0
  • USXGMII spec version 2.5 for multi port and 2.2 for single port
  • USGMII spec version 3.0
  • RGMII spec version 2.6
  • RMII spec version 1.2

 

Protocol Features

FEATURE NAME

DESCRIPTION

100Gbps Interfaces

100Gbps Ethernet interfaces based on IEEE 802.3-2015 and IEEE 802.3cd 

  • Supports CGMII
  • Supports 100GBase-R PCS and PMA
  • Supports PMD interfaces
    • 100GBase-CR10/100GBase–SR10
    • 100GBase-CR4/100GBase-KR4/100GBase-KP4
    • 100GBase-KR2/100GBase-CR2/100GBase-SR2
    • 100GBase-DR
  • Supports RS FEC
  • Supports fire-code FEC
  • Supports PMD training
  • Supports backplane auto-negotiation
  • Supports Energy Efficient Ethernet
50Gbps Interfaces

50Gbps Ethernet interfaces based on IEEE 802.3cd_D3p0 and 25/50 Gigabit Ethernet Consortium

  • Supports 50GMII
  • Supports 50Gbase-R PCS and PMA
  • Supports fire-code FEC
  • Supports RS FEC
  • Supports PMD interfaces: 50GBase-KR/50GBase-CR/50GBase-S
  • Supports back-plane auto-negotiation
  • Supports PAM4/NRZ lane encoding/decoding
  • Energy Efficient Ethernet
40Gbps Interfaces  

40Gbps Ethernet interfaces based on IEEE 802.3-2015

  • Supports XLGMII
  • Supports 40GBase-R PCS and PMA
  • Supports fire-code FEC
  • Supports PMD interfaces: 40GBase-KR4/40GBase-CR4/40GBase-SR4
  • Supports backplane auto-negotiation
  • Supports Energy Efficient Ethernet
25Gbps Interfaces

25Gbps Ethernet interfaces based on IEEE 802.3by-2016 and 25 Gigabit Ethernet Consortium

  • Supports 25GMII
  • Supports 25GBase-R PCS and PMA
  • Supports fire-code FEC
  • Supports RS FEC
  • Supports PMD interfaces: 25GBase-CR/25GBase-KR
  • Supports back-plane auto-negotiation
  • Supports Energy Efficient Ethernet
10Gbps Interfaces

10Gbps Ethernet interfaces based on IEEE 802.3-2015

  • Supports XGMII
  • Supports 10GBase-R and XSBI PCS and PMA
  • Supports 10GBase-KR/10GBase-KX4
  • Supports XAUI, RXAUI
  • Supports fire-code FEC for 10GBase-KR
  • Supports PMD training
  • Supports backplane auto-negotiation for 10GBase-KX4 and 10GBase-KR
  • Energy Efficient Ethernet
  • USXGMII interfaces: Single port and Multi port (without RS-FEC)
1Gbps Interfaces

1Gbps Ethernet interfaces based on IEEE 802.3-2015

  • Supports GMII
  • Supports 1000Base-KX
  • Supports TBI 
  • Supports USGMII 
    • SGMII
    • QSGMII
    • OSGMII
  • Supports RGMII
  • Supports clause 73 backplane auto-negotiation
  • Supports clause 37 auto-negotiation
  • Supports full duplex and half duplex of operation
  • Energy Efficient Ethernet
10/100Mbps Interfaces

10/100Mbps Ethernet interfaces based on IEEE 802.3-2015

  • Supports MII
  • Supports RMII
Dynamic Switching Supports run-time speed switching
PMA Bus-Width

Supports configurable PMA bus width: 2, 4, 8, 10, 16, 20, 32, 40, 64, 66, and 80 bits

Clock, Jitter, Drift
  • Support for external clock mode

  • Supports CDR for serial interfaces

  • Support for internal clock mode for parallel bus-width interfaces

  • Jitter and skew support in internal clock mode

  • Auto-detection and correction of clock frequency drift in internal clock mode

Flow Control

Supports Pause FC and PFC pause FC

Frame Types

Supports the following frame types:

  • Ethernet IEEE 802.3 (Type and Length defined)
  • Jumbo frame
  • MAGIC frame
  • Version II frame
  • Pause frame
  • PFC Pause frame
  • Management frame
  • Tagged Frame: 
    • Single Tagged (Q-VLAN tag)
    • Double tagged (S-VLAN tag and Q-VLAN tag)
  • Upper Layer Frames:
    • TCP
    • UDP
    • IPV4
    • IPV6
    • SNAP
    • MPLS
    • FC
    • MACSEC
Custom Frame  Proprietary header support
MDIO Interface  Supports MDIO interface as per Clause 22 and Clause 45

 

Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage
  • Callback-based error injection capability for creation of illegal stimulus from the VIP
  • Predefined protocol checkers to verify the compliance of the MAC and PHY layers of the DUT model to protocol requirements
  • Monitor agent with analysis ports which can be used for scoreboarding purpose

 

Other Supported Features

Simulator Support

IUS, XT, VCS, and MTI

Testbench Language Interfaces

SystemVerilog and e

Methodology

UVM, up to version 1.2

OVM

Trace Debug

Yes

Functional Coverage - SystemVerilog

Yes

iPDA for Easy Debugging

MAC Layer

Dynamic Activation

Yes

RapidCheck

Yes

 

Supported Design-Under-Test Configurations

MAC PHY Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck

 

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Training