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VIP for Ethernet Base-T1

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for the Ethernet Base-T1 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for Base-T1 Ethernet helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Base-T1 Ethernet runs on all major simulators and supports SystemVerilog language along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

The VIP for Base-T1 Ethernet enables verification of Ethernet interfaces in standalone, partial stack, and full stack mode for speeds of 100Mbps and 1000Mbps:

  • XMII level, that is, between MAC and PHY
  • Between PHY sub-layers, that is, PCS and PMA
  • Between link partners, that is, TX Station and RX Station

The VIP for Base-T1 Ethernet complies with IEEE 802.3 Ethernet standards and draft specifications. It supports other widely popular Ethernet interfaces, which are proprietary and based on IEEE 802.3.

Specification Support

  • IEEE 802.3bw-2015 (26 October 2015)
  • IEEE 802.3bp-2016 (30 June 2016)

Feature Highlights

Feature Name


100 Base-T Interface 100 Base-T1 Ethernet interface based on IEEE 802.3bw-2015
  • Supports MII
  • Supports 100 Base-T PCS
1000 Base-T Interface 1000 Base-T1 Ethernet interface based on IEEE 802.3bp-2016
  • Supports GMII
  • Supports 1000 Base-T1 PCS (including 80/81B Encoding, RS FEC (450, 406), EEE)
Dynamic Switching Supports run-time speed switching
PMA Bus-Width Supports configurable PMA bus width: 2 bits
Clock, Jitter, Drift
  • Support for external clock mode
  • Support for internal clock mode for parallel bus-width interfaces
Flow Control Supports Pause FC and PFC pause FC
Frame Types Supports the following frame types:
  • Ethernet IEEE 802.3 (Type and Length defined)
  • Jumbo frame
  • MAGIC frame
  • Version II frame
  • Pause frame
  • PFC Pause frame
  • Management frame
  • Tagged Frame:
    • Single Tagged (Q-VLAN tag)
    • Double tagged (S-VLAN tag and Q-VLAN tag)
  • Upper Layer Frames:
    • TCP
    • UDP
    • IPV4
    • IPV6
    • SNAP
    • MPLS
    • FC
    • MACSEC
Custom Frame Proprietary header support
MDIO Interface Supports MDIO interface as per Clause-22 and Clause-45

Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage
  • Callback-based error injection capability for creation of illegal stimulus from the VIP
  • Predefined protocol checkers to verify the compliance of the MAC and PHY layers of the DUT model to protocol requirements
  • Monitor agent with analysis ports that can be used for scoreboarding purpose
  • Transaction tracker: Configurable tracking of all the transactions on the channels

Other Supported Features

Simulator Support IUS, XT, VCS, and MTI
Testbench Language Interfaces SystemVerilog
Methodology UVM, up to version 1.2
Trace Debug Yes
Functional Coverage - SystemVerilog Yes
Dynamic Activation Yes
RapidCheck Yes