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VIP for FlexE

The Cadence® Verification IP (VIP) for Flexible Ethernet (FlexE) provides a mature, highly capable compliance verification solution for the FlexE protocol stack incorporating bus functional model (BFM) and integrated protocol checkers and coverage. The VIP for FlexE is designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels helping to reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP for Ethernet FlexE is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.


  • OIF FLEXE-02.1(2019) specification
  • IEEE 802.3-2018


Protocol Features



OIF FLEXE-02.1(2019)

  • Channelization/Bonding/Sub-Rating/Hybrid
  • Multiple 50G/100G/200G/400G BaseR PHY
  • FlexE clients of 5G, 10G, 25G, 40G, 50G, 100G, 200G, and 400G speeds
  • Maximum number of FlexE clients supported: 80
  • Maximum number of BaseR PHY supported: 8
  • 5G and 25G granularity
  • Calendar A/B
  • Calendar Resizing
  • Padding and Interleaving
  • Management and Synchronization frames
PMA Bus-Width

Supports Bus Width: 1, 2, 4, 10, 16, 20, 32, 40, 64, 66, 80, 120, 128, 160

Frame Types

Supports the following frame types:

  • Ethernet IEEE 802.3 (type and length defined)
  • Jumbo frame
  • MAGIC frame
  • Version II frame
  • Tagged Fframe: 
    • Single tagged (Q-VLAN tag)
    • Double tagged (S-VLAN tag and Q-VLAN tag)
  • PTP
Custom Frame Supports proprietary header

Supports Single Clock mode (External)

Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage
  • Callback-based error injection capability for creation of illegal stimulus from the VIP
  • Predefined protocol checkers to evaluate the compliance of the DUT model to protocol requirements
  • Monitor agent with analysis ports to be used as hooks for integrity scoreboard
  • Transaction tracker: Configurable tracking of all the transactions on the channels


Other Supported Features

Simulator Support IUS, XM, VCS, and MTI
Testbench Language Interfaces SystemVerilog
Methodology Support Universal Verification Methodology (UVM)

Functional Coverage - SystemVerilog


Trace Debug


UVM Agent Yes