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VIP for DisplayPort 8K

Incorporating the latest protocol updates, the mature and comprehensive Cadence® Verification IP (VIP) for DisplayPort 8K (8.1Gpbs per lane) provides a complete bus functional model (BFM) with integrated automatic protocol checks. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP for DisplayPort helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The Cadence VIP for DisplayPort 8K is compatible with all main verification languages (such as Verilog, System Verilog, e, VHDL, C, SystemC®, and Vera) and industry-standard methodologies (such as UVM, OVM, VMM), and runs on all leading simulators.

Specification Support

The VIP for DisplayPort 8K provides support for to the following VESA specifications: DisplayPort versions 1.2a, 1.3, 1.4, and 1.4a and Embedded DisplayPort (eDP) versions 1.3, 1.4, 1.4a, and 1.4b.

The specifications are available at http://www.vesa.org.

Protocol Features

The Cadence VIP for DisplayPort 8K is the industry’s most comprehensive protocol validation solution for predictable verification of DisplayPort designs. The VIP for DisplayPort 8K includes a configurable BFM, protocol monitor, and library of integrated protocol checks. The VIP for DisplayPort 8K is architected to enhance design verification productivity, ensure high-quality designs, and deliver maximum performance.

Supported Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
DisplayPort 1.2a
Number of Main Link Lanes Supports x1, x2, and x4 lane configurations
Link Rate Models High Bit Rate 2 (HBR2) 5.4Gbps, High Bit Rate (HBR) 2.7Gbps, and Reduced Bit Rate (RBR)1.62Gbps modes
DPCD Provides support for DisplayPort Configuration Data (DPCD) v1.2
HPD Supports HPD plug, unplug, hot plug, and IRQ
AUX Supports Native AUX and I2C-over-AUX
Enables AUX Manchester-II encoding, start and stop conditions
Provides support for AUX jitter generation and detection
SST Supports isochronous transport services in Single-Stream Transport mode
MST Supports isochronous transport services in Multi-Stream Transport mode
Video Handles all bit depth via pixel arrays and supports color formats
Audio Native support for LPCM non-HBR, LPCM HBR, INFOFRAME SDP, and Audio_TimeStamp SDP
MSA/SDP Enables insertion and verification of Main Stream Attributes (MSA) and Secondary Data Packet (SDP)
Interlaced Video Mode Support Interlaced Video Mode
Enhanced Framing Supports both basic framing as well as enhanced framing with increased robustness
ECC Supports secondary data Error Correcting Code (ECC)
CRC Support calculating 16-bit CRC for each color component
Link Quality Test Supports link quality measurement patterns Nyquist, Symbol Error Rate, PRBS7, Custom 80 Bit, and HBR2 EYE pattern
Link Training Full link training and status monitor, including clock recovery and channel equalization sequences
Adjustable link rates, number of lanes, drive voltage swing levels, and pre-emphasis levels
Enables link re-training on loss of clock lock, symbol lock, or inter-lane alignment
Main Link Physical Layer Provides main link scrambling/descrambling, ANSI 8B10B encoding/decoding, serialization/deserialization, skewing/deskewing, FEC
Main Link - Link Layer Provides frames, lines, Idles, color packing/unpacking, stuffing/un-stuffing, framing/un-framing, rate-governing, MTP, etc.
Power Management Enables Sink power state machine and power-save mode
Global Time Code Enabled synchronization between DP devices across a DP link to a 100ns precision
DP1.3, DP1.4, and DP 1.4a
Video Format Update Supports YCbCr 4:2:0
Supports RAW bpp 6, 7, 8, 10, 12, 14, 16
Supports Adaptive-Sync and ignore MSA
Supports MISC 1-bit 6 support
SDP Format Update Supports Camera SDP
Supports VSC SDP extension for Pixel Encoding and Colorimetry Format
Supports Video Stream Configuration Extension VESA (VSC_EXT_VESA) chain-able SDP type
Supports Video Stream Configuration Extension CEA (VSC_EXT_CEA) chain-able SDP type
Supports CEA InfoFrame SDP packing format Ver.1.3
Supports Picture Parameter Set SDP
Supports SDP Splitting in SST and MST mode
Audio Format Update Native support for 3D LPCM, One Bit, and DST types
Forward Error Correction (FEC) Supports Reed-Solomon code FEC function RS (254, 250)
Supports FEC encoding in DPTX and FEC decoding in DPRX
Supports two-way interleaving, CD_ADJ, FEC_PM
Supports enabling/disabling FEC
Supported for Lanes (1, 2 or 4) with SST, MST with or without HDCP
FEC SCRs Supports FEC decode enable sequence re-enable 1,000LL
Supports FEC enable sequence first enable 1,000LL after LT
Supports FEC decode sequence insertion at the end of FEC block
Support PM symbol not to advance the HDCP cipher
Supports FEC running disparity change
Link Training Update (+SCRs) Supports 8.1Gbps/lane speed
Supports TPS4 pattern
Supports Post-Link training request sequence and fallback support
Supports a total of 10 AUX_ACKs for read request
Supports only lowest numbered lane CR done
Supports Symbol lock failures in 2- and 4-lane configurations
Supports reduced lane fallback during CR
Supports the last partial TPS2/TPS3/TP4 training patterns
Link Quality Measurement Pattern Update Supports CP2520 (HBR2 Compliance EYE pattern) SR-CP-CP-SR-248 00h's
Supports CP2520 (HBR2 Compliance EYE pattern) SR-BF-BF-SR-248 00h's
Supports CP2520 (HBR2 Compliance EYE pattern) SR-BS-BS-SR-248 00h's
Added register at DPCD Address 0025Bh
Link Training-Tunable PHY Repeater Source and Sink model support LTTPR
eDP 1.3
Backlight Control Enables Backlight and Display control registers
Display Authentication Supports Alternative Scrambler Seed Reset (ASSR)
Fast Training Supports fast training without AUX handshakes
PSR/PSR2 Provides the ability for Panel Self Refresh (PSR)
eDP 1.4
ALPM Supports Advanced Link Power Management (ALPM) to reduce wakeup latency
Link Rate Supports new standard link rates: R216 (2.16Gbps), R243 (2.43Gbps), R324 (3.24Gbps), and R432 (4.32Gbps) for system optimization
Voltage Swing Supports increased voltage swing range, allowing lower swing levels
Aux Frame Sync AUX-based Source-to-Sink Device Active Video Timing Synchronization (Initial release)
eDP 1.4a and eDP 1.4b
ALPM Update Supports ALPM as requirement for PSR2 operation and that the ALPM Enable bit must be set for PSR2 operation
Supports PM_State 2a optional for Sink devices
Supports transmitter requirements with regard to starting ML_PHY_LOCK signal (except IDLE pattern)
Supports fast wake timing and entry for Main-Link lock setup time tML_PHY_LOCKsu
Supports last partial ML_PHY_LOCK pattern
PSR State Update Updated to include transition from any active state to State 1 in Figure 6-4
Updated to include transition from PSR_State 1 to PSR_State 3 in Figure 6-5
Updated to clarify the transition from PSR_State 1 to PSR_State 2
Update to include transition from any active state to State 0 in Figure 6-5
Supports the timing of single frame update immediately after PSR entry
Support for Y-coordinate
Supports the updated table for possible control bit setting combinations
Supports the defined new selective update X and Y coordinate increment granularity limits
Supports the updated timing that CRC for the PSR2 SU can be sent and Source device can enter PM State 2a or 3a
Supports the redefined synchronization latency in Sink device in Table 6-7
AUX Frame Sync Update Removed many of the device requirements for GTC, as specified in DP v1.3
Supports DPCD Address 00117h, expanded value of 1 description
Supports that AUX Frame Sync and GTC are not required for PSR2 when not making selective updates
Supports the better-defined AUX Frame Sync activation and deactivation
HDCP 1.3
Authentication Supports HDCP 1.3 Authentication Protocol
Link Integrity Check Supports link integrity check in SST and MST modes
HDCP Cipher Supports HDCP 1.3 cipher and data encryption/decryption
Encryption Status Signaling Supports encryption signaling in SST and MST modes
HDCP 2.2
Authentication Supports HDCP 2.2 Authentication Protocol
Link Integrity Check Supports link integrity check in SST and MST modes
HDCP Cipher Supports HDCP 2.2 cipher and data encryption/descryption
Encryption Status Signaling Supports encryption signaling in SST and MST modes

Key Verification Capabilities 

  • Plugs into existing verification environments

  • Rapid testbench integration reduces time to first test

  • Incorporates expertise acquired through many prior applications

  • Accelerates protocol compliance verification

  • Models both Source and Sink

  • Includes both Active (Bus Functional Model) BFM and Passive (Monitor) models

  • Builds around layers and queues allowing strong flexibility to fully control over all transactions taken place in the model

  • Creates SOMA configuration for functionality and timing with the PureView tool
    • Parameters defined in the DisplayPort specification, such as model types, DPCD capabilities, etc. 
    • Parameters provided for ease of use and verification purpose such as IDLE packet length, etc.
  • Provides simulation-level configuration file, .denalirc, with keyword/value pairs to globally control the models

  • Enables callback capabilities to support intelligent user-defined testbenches
    • Packet callbacks are triggered whenever a packet is moving across a layer, can be used to "scoreboard" check or to inject errors
    • Memory/register callbacks are triggered whenever memory is accessed without polling
  • Provides flexible register interfaces:
    • Model-specific registers allow for real-time status and model simulation control such as behaviors, error severities, etc. 
    • Protocol configuration DPCD/EDID registers manipulated with the AUX read/write as well as backdoor read/write
  • Provides for powerful error injection capability to simulate how the DUT would react to real-world errors
    • Predefined error injections such as AUX response corruption, Manchester-II filed length/pattern errors, etc. 
    • User-defined error injections via callbacks
  • Enables bypass of training mode to link devices instantly

  • Handles error detection, reporting, logging, and complete checking of protocol rules

  • Operates in both simulated and accelerated platforms for ultimate flexibility

  • Interface choice: Serial and Parallel (10-bit, 20-bit, and 40-bit for MainLink only)

Other Supported Features

Testbench Language Interfaces

SystemVerilog, e, Verilog, VHDL, and C/C++

Simulator Support IES, VCS, and MTI
Methodology Support Universal Verification Methodology (UVM), OVM, and VMM

UVM Agent


Trace Debug


Assertion Coverage Yes

Functional Coverage - SV






Transaction Log


Supported Design-Under-Test Configurations

Master Slave Full Stack

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments