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VIP for DisplayPort 2.0

The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K. Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The VIP for DisplayPort 2.0 is compatible with all main verification languages such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera; and methodologies such as UVM, OVM, and VMM; and runs on all leading simulators.

Specification Support

The Cadence VIP for DisplayPort 2.0 supports the following VESA specifications: 

  • DisplayPort versions 1.2a, 1.3, 1.4, 1.4a, and 2.0

  • Embedded DisplayPort (eDP) versions 1.3, 1.4a, 1.4b, and 1.5

The specifications are available at http://www.vesa.org.

Product Highlights

The Cadence VIP for DisplayPort 2.0 is a comprehensive protocol validation solution for predictable verification of DisplayPort designs. The VIP for DisplayPort 2.0 includes a configurable BFM, protocol monitor, and library of integrated protocol checks. The VIP for DisplayPort 2.0 is created to enhance design verification productivity, ensure high-quality designs, and deliver maximum performance.

Feature Name
DisplayPort 2.0 (without FEC)


128b/132b channel encoding


Scrambling/descrambling for new block encoding

Link Rate

Models new link rates: Ultra high bit rate 10 (UHBR10) 10Gbps/lane

Control Data Indicator

CDI insertion

Combine 4-bit CDI + four 32-bit symbols to 132-bit symbols


Precoding + decoding of precoding


Serialization/deserialization of 8b/10b and 128b/132b encoding


TX skew (up to 32-bit between lanes)

RX deskew

eDP 1.5

Content Protection

TPS4 with Alternative Scrambler Seed Reset (ASSR)

ALPM Update

Removed ALPM requirement for DSC and eDP devices

HDR Support Update

New SDP packets to support HDR (VCS Extension VESA SDP and VCS Extension CEA SDP)

SDP Format Update

SDP splitting for SST mode

Key Features

The following table describes key features from the specification that are implemented in the VIP.

Key Verification Capabilities

  • Plugs into existing verification environments
  • Rapid testbench integration reduces time to first test
  • Incorporates expertise acquired through many prior applications
  • Accelerates protocol compliance verification
  • Models both Source and Sink
  • Includes both Active (Bus Functional Model) BFM and Passive (Monitor) models
  • Builds around layers and queues allowing strong flexibility to fully control over all transactions taken place in the model
  • Creates SOMA configuration for functionality and timing with the PureView tool
    • Parameters defined in the DisplayPort specification, such as model types, DPCD capabilities, etc.
    • Parameters provided for ease of use and verification purpose such as IDLE packet length, etc.
  • Generates constrained-random bus traffic over three channels:
    • Main Link: Active Video, Secondary Data Packet, IDLE packet, ML Power-Down signals
    • AUX: Native AUX, I2C AUX, Manchester Transactions, AUX_PHY signals
    • HPD: plug, unplug, hot plug, and IRQ pulse
  • Provides simulation-level configuration file, .denalirc, with keyword/value pairs to globally control the models
  • Enables callback capabilities to support intelligent user-defined testbenches
    • Packet callbacks are triggered whenever a packet is moving across a layer, can be used to "scoreboard" check or to inject errors
    • Memory/register callbacks are triggered whenever memory is accessed without polling
  • Provides flexible register interfaces:
    • Model-specific registers allow for real-time status and model simulation control such as behaviors, error severities, etc. 
    • Protocol configuration DPCD/EDID registers manipulated with the AUX read/write as well as backdoor read/write
  • Provides for powerful error injection capability to simulate how the DUT would react to real-world errors
    • Predefined error injections such as AUX response corruption, Manchester-II filed length/pattern errors, etc.
    • User-defined error injections via callbacks
  • Enables bypass of training mode to link devices instantly
  • Handles error detection, reporting, logging, and complete checking of protocol rules
  • Interface choice: Serial and Parallel (10-bit, 20-bit, and 40-bit for MainLink only)

 Other Supported Features

UVM Agent Yes
Trace Debug Yes
Assertion Coverage Yes
Functional Coverage - SV Yes
RapidCheck Yes
TripleCheck Yes
Transaction Log Yes

Supported Design-Under-Test Configurations

Master Slave Full Stack

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments