Home: IP Portfolio > Verification IP > Simulation VIP > VIP for Display Stream Compression (DSC)

VIP for Display Stream Compression (DSC)

The Cadence® Verification IP (VIP) for Display Stream Compression (DSC) provides an ability to perform comprehensive verification of DSC-related features of display protocols. 

This product complements the Cadence VIP for MIPI DSI and VIP for DisplayPort and must be used with one of them.

The Cadence VIP for DSC is compatible with all main verification languages (such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera) and industry-standard methodologies (such as UVM, OVM, VMM), and runs on all leading simulators.

Specification Support

The Cadence VIP for DSC supports DSC 1.2a for Embedded DisplayPort (eDP) version 1.4b.

The Cadence VIP for DSC supports DSC 1.1 (and optionally DSC 1.2 for out-of-spec implementations) for the MIPI Display Serial Interface protocols family, DSI 1.3.1, and DSI-2 1.0.

The specifications are available at http://www.vesa.org.

Protocol Features

Cadence VIP are the industry’s most comprehensive protocol validation solutions for predictable verification of DSC designs. The VIP include a configurable BFM, protocol monitor, and library of integrated protocol checks. The VIP are architected to enhance design verification productivity, ensure high-quality designs, and deliver maximum performance.

Key Features

Feature Name
Description

eDP 1.4b

DSC Version

DSC 1.2a (VBR is not supported by the DP specification)

Configuration

Discovery, Enabling, Disabling 

Framing and Compressed Stream Mapping

1, 2, 4, 8, 12, 16, 20, 24 slices per line

Picture Parameter Set (PPS) Packet

PPS packet header and payload

DSC DPCD Fields

All DSC related registers are supported

PSR in DSC

PSR SDP and PSR2 Selective Update in DSC Configuration

MIPI DSI and DSI-2

DSC Version DSC 1.1
Decoding Process Video frames encoded using Display Stream Compression algorithm are decoded by VIP monitor
Encoding Process Active Processor VIP generates video frames encoded using Display Stream Compression algorithm
Format of DSI Packets Related to DSC VIP verifies format correctness of DSI packets related to Display Stream Compression
Content of DSI Packets Related to DSC VIP verifies content correctness of DSI packets related to Display Stream Compression

Key Verification Capabilities

  • Plugs into existing verification environments
  • Rapid testbench integration reduces time to first test
  • Accelerates protocol compliance verification
  • Includes both Active (Bus Functional Model) BFM and Passive (Monitor) models
  • Display Stream Compression parameters can be configured as a part of SOMA configuration with the PureView tool
  • Handles error detection, reporting, logging, and complete checking of protocol rules
  • Operates in both simulated and accelerated platforms for ultimate flexibility

Other Supported Features

Testbench Language Interfaces

SystemVerilog, e , Verilog, VHDL, and C/C++

Simulator Support IES, VCS, and MTI
Methodology Support Universal Verification Methodology (UVM), OVM, and VMM

UVM Agent

Yes

Trace Debug

Yes

Supported Design-Under-Test Configurations

Master Slave Full Stack

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

Training