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VIP for CoaXPress

The mature and comprehensive Cadence® Verification IP (VIP) for CoaXPress incorporates the latest protocol updates to provide a complete bus functional model (BFM) with integrated automatic protocol checks. The VIP for CoaXPress is designed for easy integration in testbenches at IP, SoC, and system levels to help engineers reduce time to first test, accelerate verification closure, and ensure quality of end product.

The Cadence VIP for CoaXPress is compatible with the following:

  • Main verification languages such as Verilog, SystemVerilog, e, VHDL, C, SystemC®, and Vera
  • Industry-standard methodologies such as UVM, OVM, and VMM
  • Runs on all leading simulators

Specification Support

The VIP for CoaXPress supports version(s) 1.0, 1.1, and 1.1.1 of the specification.

The specification is available at http://jiia.org/en.

Product Highlights

The following table describes key features from the specifiation that are implemented in the VIP for CoaXPress.

Feature Name
New Feature


Supports up to 16 connections, up to 16 devices

Yes 11.30.053

Bit Rates

  • 1.250Gbps
  • 2.500Gbps
  • 3.125Gbps
  • 5.000Gbps 
  • 6.250Gbps
Yes 11.30.053
Bootstrap Registers Supports Bootstrap registers Yes 11.30.053
Device Discovery Supports Device Discovery process Yes 11.30.054


Supports 8B10B encoding and decoding for up connections and down connections

Yes 11.30.053
Triger Supports Trigger and I/O - Trigger acknowledgment  Yes 11.30.053
IDLE Supports IDLE packet Yes 11.30.053
Control Data
  • Control commands: memory read, memory write, control channel reset
  • Control ack: final, wait, logical errors, and others
  • Max Control Size
Yes 11.30.053
Stream Data
  • Supports stream data packing
  • Stream markers
  • Link framing
  • Single stream
  • Multi-steams (up to 256 streams)
  • Max data size
Yes 11.30.053
CRC Supports CRC for Steam and Control Data Yes 11.30.053
Transmission Order Supports packet transmission priority 0,1,2 Yes 11.30.053
Pixel Formats
  • Mono 
  • Bayer - all sub types
  • RGB
  • RGBA
  • YUV - all sub types
  • YcbCr601 - all sub types
  • YcbCr709 - all sub types
Yes 11.30.053
Scan Modes

Supports Rectangular Image Stream

Yes 11.30.053


  • Compliance Management System automates protocol compliance verification

  • Generates constrained-random bus traffic

  • Responds to bus traffic as a slave

  • Transmits snoop transactions by mimicking a dummy interconnect

  • Monitors, checks, and collects coverage on bus traffic and interconnect

  • Includes hundreds of assertions for formal compliance verification

    Supports SystemVerilog and SystemC language testbenches

  • Complies with the Unified Verification Methodology (UVM)


Simulator Support IES, VCS, and MTI

Testbench Language Interfaces

SystemVerilog  and SystemC

Methodology Universal Verification Methodology (UVM), OVM, and VMM

UVM Agent


Trace Debug

Functional Coverage - SystemVerilog


Dynamic Activation _
RapidCheck x




Supported Design-Under-Test Configurations

Source Sink Hub/Switch
Full Stack Controller Only PHY Only


Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments