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DisplayPort Simulation Verification IP (VIP)

Specification Support

The Cadence VIP for DisplayPort protocols provides support for DisplayPort 1.2 and Embedded DisplayPort (eDP) versions 1.3 and 1.4. 

The specifications are available here: http://www.vesa.org

Key Features

Feature Name
DisplayPort 1.2


Supports Native AUX and I2C-over-AUX
Enables AUX Manchester-II encoding, start and stop conditions
Provides support for AUX jitter generation and detection

Bit Depth

Handles all pixel bit widths

DPCD Provides support for DisplayPort Configuration Data (DPCD) v1.2
ECC Supports secondary data Error Correcting Code (ECC)
Enhanced Framing Supports both basic framing as well as enhanced framing with increased robustness
HPD Supports HPD plug, unplug, hot plug, and IRQ
Link Quality Test Supports link quality measurement patterns Nyquist, Symbol Error Rate, PRBS7, Custom 80 Bit and HBR2 EYE pattern

Link Rate

Models High Bit Rate 2 (HBR2) 5.4Gbps, High Bit Rate (HBR) 2.7Gbps, and Reduced Bit Rate (RBR)1.62Gbps modes

Link Training

Full link training and status monitor, including clock recovery and channel equalization sequences
Adjustable link rates, drive voltage swing levels, and pre-emphasis levels
Enables link re-training on loss of clock lock, symbol lock, or inter-lane alignment
Main Link Link Layer Supports isochronous transport services in Single Stream Transport (SST) mode

Main Link Physical Layer

Provides main link scrambling and de-scrambling, ANSI 8B10B encoding/decoding, serialization, and deserialization


Enables insertion and verification of Main Stream Attributes (MSA) and Secondary Data Packet (SDP)
Number of Main Link Lanes Supports x1, x2, and x4 lane configurations
Power Management Enables Sink power state machine and power-save mode
eDP 1.3
Backlight Control Enables Backlight and Display control registers
Display Authentication Supports Alternative Scrambler Seed Reset (ASSR)

Fast Training

Supports fast training without AUX handshakes
PSR/PSR2 Provides the ability for Panel Self Refresh (PSR)
eDP 1.4
ALPM Supports Advanced Link Power Management (ALPM) to reduce wake latency

Link Rate

Supports new standard link rates: R216(2.16Gbps), R243(2.43Gbps), R324(3.24Gbps) and R432(4.32Gbps) for system optimization
Votage Swing Supports increased voltage swing range, allowing lower swing levels

Supported Design-Under-Test Configurations

Source Sink Hub/Switch
Full Stack Controller Only PHY Only

Test Suite Options

Basic CMS PureSuite TripleCheck


Test Suite Comparison

Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments