Home: IP Portfolio > Verification IP > Simulation VIP > VIP for SWD (Serial Wire Debug)

VIP for SWD (Serial Wire Debug)

The Cadence® Verification IP (VIP) for SWD provides support for the Serial Wire Debug protocol, which is part of the Arm® Debug Interface specification. It provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for SWD is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

Specification Support

The VIP for SWD supports Version 1 and Version 2 of the SWD protocol as per Arm Debug Interface specification v6.0 (ADIv6.0).

Product Features

Key features from the specification implemented in the VIP are shown in the table below.

FEATURE NAMEDESCRIPTION

Serial Wire Debug Port

Fully supports SWD-DP functionality as per section B4 of ADIv6.0 specification

Serial Wire/JTAG Debug Port

Fully supports SWD-related functionality of SWJ-DP as per section B5 of ADIv6.0 specification, including customizable JTAG/SWD switching mechanism

 

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the SWD protocol rules

  • Coverage: Monitors, checks, and collects coverage at the transaction level

  • Error injection: Ability to inject errors at the single-bit level (Parity, Start bit, Park bit, and so on.)

  • SV UVM is fully supported, including the UVM configuration class

FEATURE NAMeDESCRIPTION

Testbench language interfaces

SystemVerilog, C++

Simulator support

IES, VCS, and MTI

Methodology support

Universal Verification Methodology (UVM)

Functional Coverage - SystemVerilog

Yes

Functional Coverage - SV

Yes

Trace Debug

Yes

TripleCheck