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VIP for AMBA ACE (includes AXI VIP, APB VIP)

This Cadence® Verification IP (VIP) provides support for the ACE specification, which is part of the Arm® AMBA® family of protocols. The VIP provides a highly capable simulation-based compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for AMBA ACE is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

The AMBA protocol is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in an SoC. It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals. The AMBA protocol promotes design reuse by defining a common backbone for SoC modules using specifications for the CHI, ACE, AXI, AHB, and APB extensions.

The AMBA ACE interface provides a framework for system-level coherency. The AMBA AXI interface supports high-performance, high-frequency system designs for communication between master and slave components.

The VIP for AMBA ACE supports ACE, ACE-Lite, ACE5, ACE5-Lite, and ACE5-LiteDVM interfaces.

The VIP for AMBA AXI supports AXI3, AXI4, AXI4-Lite, AXI5, and AXI5-Lite interfaces.

Specification Support

VIP for AMBA ACE supports the Issue F of AMBA AXI and ACE protocols.

The specifications for the AMBA protocol are available at AMBA Specifications.

See also: 

Product Highlights

Key features from the specification implemented in the VIP are shown in the table below.

Feature Name
Description
ACE-Lite Support
Allows ACE-Lite configuration; automatically modify the agent accordingly
All Data and Address Widths
Supports all legal data and address widths
AXI Support
Supports the entire AXI specification, all AXI transactions can be sent and monitored
Automatic Slave Responses
Configurable option to use automatic slave responses
Barrier Transactions
Supports monitoring and driving of Barrier transactions
Cache Model
Cache model in both active and passive agents including cache state checks
Controlling Order in Channels
User can control the order of transmission of read transfers and write responses
Data Before Address Mode
Supports sending of data before address transactions when legal
Delay Control on All Channels
Set the delay between the items on the channels
DVM Transactions
Supports monitoring and driving of DVM transactions
Exclusive Access
Supports monitoring and driving of all exclusive transactions
Low-Power Interface Support
Supports both LPI controller and LPI peripheral agents
Master Burst Signals Control
Determines the values of the signals in the read and write address channel
Master Transfer Signals Control
Determines the values of the signals in the snoop response channel
Master Snoop Signals Control
Determines the values of the signals in the snoop address channel
Multiple Agents Support
Can support any number of agents
Slave Response Control
Determines the values of the signals in the read data channel
Snoop Filter Support
Supports connection to a snoop filter
Supports All Protocol Transaction Types
Supports monitoring and driving of all read and write transactions
Atomic Transactions
Applicable to AXI5, ACE5-Lite , and ACE5-LiteDVM
Cache Stashing
Applicable to ACE5-Lite and ACE5-LiteDVM
Deallocating Transactions
Applicable to ACE-Lite and ACE5-LiteDVM
Cache Maintenance for Presistence
Applicable to ACE5, ACE5-Lite, and ACE5-LiteDVM
Data Checking and Poison
Applicatble to AXI5, AXI5-Lite, ACE5, ACE5-Lite, and ACE5-LiteDVM
Trace Signals Applicable to AXI5, AXI5-Lite, ACE5, ACE5-Lite, and ACE5-LiteDVM
User Loopback Signaling Applicatble to AXI5,ACE5-Lite, and ACE5-LiteDVM
QoS Accept Applicable to AXI5, ACE5, ACE5-Lite, and ACE5-LiteDVM
Wake-Up Signaling Applicable to AXI5, AXI5-Lite, ACE5, ACE5-Lite, and ACE5-Lite DVM
Coherency Connection Signaling Applicable to ACE5 and ACE5-LiteDVM
Distributed Virtual Memory Extensions for Armv8.1 Supports Armv8.1 architecture
Untranslated Transactions Applicable to AXI5, ACE5, ACE5-Lite, and ACE5-LiteDVM
Non-Secure Access Identifiers Applicable to AXI5, ACE5, ACE5-Lite, and ACE5-LiteDVM

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the protocol rules defined in the AXI Protocol 2.0 Specification
  • Coverage: Monitors, checks, and collects coverage on bus traffic and interconnect
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate
  • Error injection: Random
  • Interconnect Validator connection
  • Memory monitoring: Memory can be set and queried using backdoor access
  • Platforms: Operates in both simulated and accelerated platforms for ultimate flexibility
  • Random error injection promotes easy testing of scenarios
  • Slave memory emulation
  • ACE Master cache emulation
  • Traffic: 
    • Generates or emulates ACe traffice, can generate or emulate both master and slace traffic
    • Generates constrined-random bus traffic
    • Responds to bus traffic as a slace
  • Transaction tracker: Configuarble tracking of all the transactions on the channels

Other Supported Features

Compliance Management System For e only
Testbench Language Interfaces
  • ACE5 - SystemVerilog
  • Ace v1.0 and v2.0 - SystemVerilog and e

 

Functional Coverage e and SystemVerilog
Interconnect Validator  Yes
TripleCheck No
Protocol Debug App Yes