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VIP for AMBA AXI (includes APB, LPI, ATB)

This Cadence® Verification IP (VIP) provides support for the AXI specification which is part of the Arm® AMBA® family of protocols. It provides a mature, highly capable simulation-based compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for AMBA AXI is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.

The AMBA protocol is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in an SoC. It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals. AMBA promotes design reuse by defining a common backbone for SoC modules using specifications for the CHI, ACE, AXI, AHB, APB, and ATB interfaces.

The AMBA family of specifications defines a set of interface protocols that, between them, cover the on-chip data traffic requirements from data-intensive processing components requiring high-data-throughput, low-bandwidth communication requiring low gate count and power and on-chip test and debug access.

The AMBA AXI protocol supports high-performance, high-frequency system designs for communication between master and slave components.

The VIP for AMBA AXI supports the AXI3, AXI4, AXI4-Lite, AXI5, and AXI5-Lite interfaces.

Specification Support

The VIP for AMBA AXI supports the Issue F of AMBA AXI and ACE Protocol.

The specifications for the AMBA protocol are available at AMBA Specifications.

See also: 

The VIP for AMBA APB supports the following official specifications:

  • AMBA 2 APB Protocol specification
  • AMBA 3 APB specification update
  • AMBA 4 APB specification update

The VIP for AMBA ATB supports the following official specifications:

  • AMBA 4 ATB Protocol specification ATBv1.0 and ATBv1.1

Product Highlights

The VIP for AMBA AXI verifies the design under test (DUT) by providing active slave and master agents for generating stimuli, and passive slave and master agents for checking the protocol and collecting coverage. The VIP for AMBA AXI can be configured as AXI3, AXI4, or AXI4-lite.

Feature Name
Description
All Data and Address Widths 
Supports all legal data and address widths
AXI4 Additional Signaling 
Supports AxQOS, AxREGION, and user-defined signals. 
AXI4 Lite Support
Allows AXI4 Lite configuration, automatically modify the agent accordingly
Automatic Slave Responses
Configurable option to use automatic slave responses
Controlling Order in Channels
User can control the order of transmission of write transfers (AXI3 only), read transfers, and write responses
Data Before Address Mode 
Supports sending of data before address transactions when legal
Delay Control on All Channels
Set the delay between the items on the channels
Exclusive Access
Supports monitoring and driving of all exclusive transactions
Locked Transactions
Supports monitoring and driving of locked transactions (AXI3 only)
Low-Power Interface Support
Supports both LPI controller and LPI peripheral agents
Master Burst Signal Control 
Determine the values of the signals in the read and write address channel
Master Transfer Signal Control
Determine the values of the signals in the write data channel
Multiple Agents Support 
Can support any number of agents
Slave Response Control
Determine the values of the signals in the read data channel
Supports All Protocol Transaction Types
Supports monitoring and driving of all read and write transactions
Atomic Transactions
Applicable to AXI5
Data Checking and Poison
Applicable to AXI5 and AXI5-Lite
Trace Signals
Applicable to AXI5 and AXI5-Lite
User Loopback Signaling
Applicable to AXI5
QoS Accept Signaling 
Applicable to AXI5
Wake-Up Signaling 
Applicable to AXI5 and AXI5-Lite
Untranslated Transactions
Applicable to AXIS
Non-Secure Access Identifiers 
Applicable to AXIS

The VIP for AMBA ATB verifies the DUT by providing active slave and master agents for generating stimuli, and passive slave and master agents for checking the protocol and collecting coverage. The VIP for AMBA ATB can be configured as ATBv1.0 or ATBv1.1.

Key Features for AMBA ATB

 
Feature Name
Description
Dynamic Activation Support The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate
All Data Widths Supports all legal data widths 
AXI4 Additional Signaling Supports AxQOS, AxREGION, and user-defined signals 
Automatic Slave Responses Configurable option to use automatic slave responses 
Delay Control on All Channels Set the delay between the items on the channels 
Low-Power Interface Support Supports both LPI controller and LPI peripheral agents 
Master Transaction Signal Control Determine the values of the signals issued by the master 
Multiple Agents Support Can support any number of agents 
Slave Response Control Determine the values of the signals issued by the slave 
Supports All Protocol Transaction Types Supports monitoring and driving of all transactions (data, flush, and sync)

 Key Verification Capabilities for AMBA AXI

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the protocol rules defined in the AXI Protocol 2.0 Specification
  • Dynamic Activation Support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate
  • Coverage: Monitors, checks, and collects coverage on bus traffic and interconnect
  • Error injection: Random
  • Interconnect Validator connection
  • Memory monitoring: Memory can be set and queried using backdoor access
  • Platforms: Operates in both simulated and accelerated platforms for ultimate flexibility
  • Random error injection promotes easy testing of scenarios
  • Slave memory emulation
  • Transaction tracker: Configurable tracking of all the transactions on the channels
  • Traffic: 
    • Generates or emulates AXI traffic, can generate or emulate both master and slave traffic
    • Generates constrained-random bus traffic
    • Responds to bus traffic as a slave

Other Supported Features for AMBA AXI

Compliance Management System For e only
Functional Coverage SystemVerilog ,e
Interconnect Validator Yes
Testbench Language Interfaces SystemVerilog, e
TripleCheck No

Key Verification Capabilities for AMBA ATB

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the protocol rules defined in the AMBA 4 ATB Protocol Specification ATBv1.0 and ATBv1.1
  • Coverage: Monitors, checks, and collects coverage on bus traffic and interconnect
  • Error injection: Random
  • Platforms: Operates in both simulated and accelerated platforms for ultimate flexibility
  • Random error injection promotes easy testing of scenarios
  • Transaction tracker: Configurable tracking of all the transactions on the channels
  • Traffic: 
    • Generates or emulates ATB traffic, can generate or emulate both master and slave traffic
    • Generates constrained-random bus traffic
    • Responds to bus traffic as a slave

Other Supported Features for AMBA ATB

Compliance Management System For e only
Functional Coverage - SystemVerilog No
Testbench Language Interfaces SystemVerilog
TripleCheck No

 

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only


Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

"Delivering advanced multi-core ARM SoCs to our customers requires leading IC design technologies. Cadence VIP for AXI4 and ACE enables us to quickly and efficiently deliver bug-free SoC designs."

– Ting Lei, Director of Cloud Computing, HiSilicon

"As the complexity of ARM partners’ designs increases year after year, successfully verifying the performance of the SoCs has become a critical imperative. The comprehensive Cadence verification IP solution for AMBA protocols has enabled our mutual customers to address this challenge while incorporating the latest ARM technology."

– Joe Convey, Director of Design Enablement, ARM