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AMBA AXI Simulation Verification IP (VIP)

Specification Support

The AXI VIP supports the AMBA® AXI Protocol v1.0 and v2.0 and the AXI as defined in the AMBA AXI Protocol Specification.
The specifications for the AMBA protocol are available at AMBA Specifications

Product Highlights

Key Features

Feature Name
Description
Dynamic Activation Support

The user can set the VIP as active or passive without changing the test bench, and determine, during run time, which instance to instantiate.

All data and address widths Supports all legal data and address widths.
AXI4 additional signaling Supports AxQOS, AxREGION, and user-defined signals.
AXI4 Lite support Allows AXI4 Lite configuration; automatically modify the agent accordingly.
Automatic slave responses Configurable option to use automatic slave responses.
Controlling order in channels User can control the order of transmission of write transfers (AXI3 only), read transfers and write responses.
Data before address mode Supports sending of data before address transactions when legal.
Delay control on all channels Set the delay between the items on the channels.
Exclusive access Supports monitoring and driving of all exclusive transactions.
Locked transactions Supports monitoring and driving of locked transactions (AXI3 only).
Low power interface support Supports both LPI controller and LPI peripheral agents.
Master burst signal control Determine the values of the signals in the read and write address channel.
Master transfer signal control Determine the values of the signals in the write data channel.
Multiple agents support Can support any number of agents.
Slave response control Determine the values of the signals in the read data channel.
Supports all protocol transaction types Supports monitoring and driving of all read and write transactions.

Supported Design-Under-Test Configurations

Master Slave Hub/Switch
Full stack Controller-only PHY-only

Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

User Feedback

“HiSilicon is a leader in ASICs and solutions for communication networks and digital media. Delivering advanced multi-core ARM SoCs to our customers requires leading IC design technologies. The Cadence VIP for AXI4 and ACE enables us to quickly and efficiently deliver bug-free SoC designs.” 
– Ting Lei, Director of Cloud Computing, HiSilicon