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VIP for AMBA 5 CHI

Specification Support

The Cadence® Verification IP (VIP) for AMBA 5 CHI provides support for the Coherent Hub Interface (CHI) spec, which is part of the Arm® AMBA® 5 family of protocols, the next generation of Arm interface standard. It provides a highly capable compliance verification solution that supports simulation platform, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for CHI is compatible with the industry-standard Universal Verification Methodology (UVM) and runs on all leading simulators.


Key Features

FEATURE NAMEDESCRIPTION

Transaction type support

Supports monitoring and driving of all protocol Opcodes, including barrier, exclusive access, and DVM.

Dummy CHI-based interconnect

When interconnect is not present, the Active Hn-F can generate snoop requests and respond to Rn-F commands.

Communication layer support

Supports link, network and protocol layer communication.

Interface support

Support for Rn-F/Rn-D/Rn-I to Hn-F/Hn-D/Hn-I/Mn and Hn-F/Hn-I/Mn to Sn-F/Sn-I.

Flow control mechanisms

Available across all RnX-to-HnX and HnX-to-SnX links.

Channel delay support

User can delay the driving of all protocol flits.
Cache model support Facilitates the role of actual cache used in a CHI Rn-F.

Cache backdoor access

Specific or random values can be sent to the cache at the beginning of a test or during run time.

Atomic transactions

Supports monitoring and driving of atomic transactions (CHI-B feature).

Stash transactions

Supports monitoring and driving of stashing transactions (CHI-B feature).

DCT and DMT

Direct Memory Transfer and Direct Cache Transfer (CHI-B feature).

De-Allocating transactions

Supports monitoring and driving of de-allocating transactions (CHI-B feature).

Poison and Data Check

Support for the optional addition of Data Check and Poison (CHI-B feature).

System Coherency Interface 

Supports System Coherency Interface, used to connect and disconnect from a coherency domain (CHI-B feature).

 

Key Verification Capabilities

  • Compliance: Contains predefined checks to verify that the DUT agents (master and slave) adhere to the protocol rules defined in the CHI Protocol Specification.

  • Coverage: Monitors, checks, and collects coverage at transaction level.

  • Dynamic Activation support: The user can set the VIP as active or passive without changing the testbench, and determine, during run time, which instance to instantiate.

  • Error injection: Random

  • Interconnect Validator connection.

  • Platforms: Operates in both simulated and accelerated platforms for ultimate flexibility.

  • Random error injection promotes easy testing of scenarios.

  • SV UVM is fully supported, including the UVM configuration class.

  • Traffic:

    • Generates or emulates CHI traffic. Can generate or emulate traffic for all CHI component types (Rn, Hn, Mn, Sn).

    • Generates constrained-random bus traffic.

    • Automatic default responds to bus traffic.

 

Other Supported Features

FEATURE NAMeDESCRIPTION

Testbench language interfaces

SystemVerilog and e
Simulator support IES, VCS, and MTI
Methodology support Universal Verification Methodology (UVM), OVM

Functional Coverage - e

Yes

Functional Coverage - SV

Yes

Interconnect Validator

Yes

Trace Debug Yes

TripleCheck

The following features are not supported by the VIP for CHI: 

  • Data Source indication - Support for Read requests to specify the source of the data (CHI-B feature).

 

Supported Design-Under-Test Configurations

Home Node Request Node
Slave Node Miscellaneous Node


Test Suite Options

Basic CMS PureSuite TripleCheck

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments