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VIP for JESD204B/C

Description

Cadence provides a mature and comprehensive Verification IP (VIP) for the JESD204 protocol. Incorporating the latest protocol updates, the Cadence® VIP for JESD204 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for JESD204 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Specification

The VIP for JESD204 supports the following specifications:

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description

Topology

Supports master or slave configuration

Clock Frequency

Supports any frequency as the VIP works on the source clock

Initial Lane Alignment

Supports enabling or disabling initial lane alignment

64-bit Sync Header

Supports transmission of all types of sync header information, such as, FEC, CRC-3, CRC-12 and command channel

Subclass

Supports subclass0, subclass1, and subclass2

Scrambling

Supports scrambling with user-specific initial seed value

Character Replacement

Supports character replacement feature with and without scrambling

Deterministic Delay

Supports deterministic delay for subclass 1 and 2

Transport Layer Parameter

Supports config/register to control transport layer features, such as CS, HD, and F

Lane Control

Supports lane ranging from 1 to 32

Lane to Lane Delay

Supports transmission and reception for cases where lanes are not aligned

Test Mode

Supports layer-wise test mode

Error Injection

Supports error injection using callbacks

Transport Layer Bypass

Supports feature to skip transport layer operation like padding tail bits

Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage
  • Callback-based error injection capability for creation of illegal stimulus from the VIP
  • Monitor agent with analysis ports, which can be used for score-boarding purpose
  • Transaction tracker: Configurable tracking of all the transactions on the channels

Other Supported Features

Testbench Language Interfaces

SystemVerilog

UVM Methodology

Up to version 1.2

Trace Debug

Yes

Functional Coverage - SystemVerilog

Yes

Training, Documentation, and Usage Information

See the Verification IP page on Verification IP Support Home.