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TripleCheck IP Validator for USB4

The Cadence® TripleCheck IP Validator for USB4 adds another layer of verification capabilities above the VIP for USB4. The TripleCheck IP for USB4 lays its foundations upon three main components:

  • The coverage model of the basic VIP

  • A comprehensive pre-packaged testsuite

  • Verification plans (vPlans) constructed to match the specification format

Track the Process

The TripleCheck IP for USB4 provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature or those in the specification. And, when we combine that with the ability of the testsuite to reach nearly every vPlan item, we verify the design effectively, easily, and methodically. In addition, using the TripleCheck IP for USB4 helps the team to assess the project's progress by simply tracking the overall coverage grade week by week.

See only what you need

The vPlans were built in accordance to the specification structure and formations, using the same sections, headlines, and quotations from the specification, so that it is easier to check corresponding sections and annotations. The vPlans consist of "perspectives", which hold a set of parameters that roughly describe the DUT. A user is able to edit the perspective to match the DUT capabilities, thus allowing the vPlan to automatically filter portions of the specification that are irrelevant for a particular design.

Reuse the existing test coverage

In situations where there is a significant chunk of legacy tests, verification engineers can leverage the coverage from this library of tests as well. The vPlan allows users to incorporate the TripleCheck IP-provided vPlan with the user's own vPlans. Moreover, the cumulative coverage from these tests as well as the TripleCheck IP's testsuite can be plotted on the same vPlan to enhance the reach of the solution according to the user's needs.


The TripleCheck testsuite for USB4 contains hundreds of self-checking tests based on the USB4 Specification.

  • These tests are mapped to vPlan sections through relevant coverage items.

  • A robust testsuite is able to run on major simulators.

  • Most of the testcases are directed with consistency in results across simulators and seeds.

  • Testcase description is present in the test list as well as documented with the step-by-step guidance for understanding the purpose and behavior of the tests.

Specification Support

The TripleCheck IP for USB4 is compliant with the USB4 Specification Version 1.0 release.

Product Features

Key features from the specification that are implemented in the VIP are listed in the table below.


vPlan Coverage Testsuite

Logical Layer

(tick) (tick) (tick)

Transport Layer

(tick) (tick) (tick)

PCI Express® (PCIe®) Adapter

(tick) (tick) (tick)

USB Adapter

(tick) (tick) (tick)

DP Adapter

(tick) (tick) (tick)

Key Verification Capabilities

The TripleCheck IP for USB4:

  • Runs on IES and VCS

  • Supports SystemVerilog UVM

  • Includes vPlan mapping of USB4 Version 1.0 RC specification

  • Maps each vPlan item to a specific test designed to stimulate that feature

  • Is easily extended to reuse existing vPlans

  • Initiates stimulus from the DUT using the Port Driver

  • Provides a comprehensive testsuite with 300+ self-checking tests

Training, Documentation, and Usage Information

  • See the Verification IP Support Home on Cadence Online Support for training, documentation, and usage information.

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