The Cadence® TripleCheck™ IP Validator for DisplayPort product provides advanced verification capabilities suite in conjunction with the Cadence Verification IP (VIP) for DisplayPort. It is a product used for ensuring the compliance of the DUT to the DisplayPort specifications through a combination of the following main components :
The Cadence TripleCheck IP Validator for DisplayPort provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature or those in the specification. When we combine that with the ability of the testsuite to reach every vPlan item, we ensure that the design works in compliance with the specifications, easily and methodically. In addition, by using a TripleCheck vPlan, the team can assess the project's progress by simply tracking the overall coverage grade week by week.
The vPlans are built in accordance to the specification document structure, using the same sections and titles from the specification so that it is easier to check corresponding sections and annotations. The vPlan consists of "perspectives"—views of the vPlan that can be customized according to the DUT behavior using a set of parameters that roughly describe the DUT. A user is able to edit the perspective to match the DUT capabilities that allow the vPlan to automatically filter out portions of the specification that are irrelevant for a particular design.
In case there is a significant chunk of legacy tests, verification engineers can leverage the coverage from this library of tests as well. The vPlan allows users to incorporate the TripleCheck-provided vPlan with the user's own vPlans. Moreover, the cumulative coverage from these tests as well as TripleCheck testsuite can be plotted on the same vPlan to enhance the reach of the solution according to customer needs.
Currently, the TripleCheck solution contains over 250 self-checking tests in the testsuite based on VESA Compliance specification for DisplayPort and HDCP.
The thorough testsuite, elaborated coverage model, and the vPlan visualization to track verification progress combined with the industry proven VIP for DisplayPort core offer a complete and monolithic solution for verification teams working on VIP for DisplayPort with consistent results when time to market is of essence.
Key features from the specification that are implemented in the VIP are listed in the table below.
Source/Sink Link Training
Source/Sink Link Maintenance
Source/Sink AUX Services
DP Video Transmission
High Bit Rate (HBR3)
IRQ HPD Operation
HDCP 1.3 TX/RX w/o Repeater
HDCP 2.2 TX/RX w/o Repeater
TripleCheck IP Validator for DisplayPort:
TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.
TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.
Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions.
TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.
The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.
In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.
MIPI CSI-2 Features
Key features from the spec that are implemented in the VIP are listed in the following table:
|Advanced error reporting||
Stimulus and coverage collection for all applicable error scenarios.
|State machines||Stimulus and coverage collection for all state machine transitions.|
|Transaction formation rules||Stimulus and coverage collection for all applicable transactions.|
|Physical layer||4 MIPI D-PHYsm or C-PHYsm data lanes for the CSI-2 receiver DUT.|
|Multi lane distribution and merging||Distribution and merging of data between data lanes.|
|Low level protocol||CSI-2 frames and packet structures.|
|Data Formats||All valid CSI-2 data types.|
|Annex C - CSI-2 recommended receiver error behavior||Error scenarios in the D-PHY, packet, and frame layers.|
|C-PHY errors||Multiple error scenarios for C-PHY physical layer.|
|MIPI CSI-2 Receiver Protocol Conformance Test Suite||The TripleCheck test suite includes the implementation of all CTS tests that are defined in CSI-2 Receiver Protocol Conformance Test Suite Version 1.01.|
|D-PHY v1.2 features||The suite supports the D-PHY 1.2 skew calibration feature (Initial and Periodic) + low-power data after triggers.|
|Physical layer||Support C-PHY and D-PHY PPI interface for both master and slave configurations.|
|UVM config suport||Supports UVM config environments for all TripleCheck flavors.|
TripleCheck VIP for CSI-2:
TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.
|Constrained-random example tests|
|Directed compliance tests|
|Constrained-random compliance tests|
|Tests targeting all protocol layers|
|3rd party simulator test execution|
|SystemVerilog functional coverage model|
|efunctional coverage model|
|Verification plan mapped to protocol specification|
|Verification plan integration with Cadence vManager metric-driven analysis system|
|Verification plan integration with 3rd party simulator environments|