The Cadence® TripleCheck™ IP Validator for MIPI® I3C adds another layer of verification capabilities above the VIP for MIPI I3C for I3C slave devices. The TripleCheck IP Validator for MIPI I3C lays its foundation on the three main components:
The vPlan was built in accordance to the specification structure and formations, using the same sections, headlines, and quotations from the specification. Overall, the vPlan contains specification quotations, each of which is related to a coverage item. The testsuite is designed for robustness and can run on any simulator with any testbench language to achieve the same result—at least 95% overall coverage score in our vPlan.
The TripleCheck IP Validator for MIPI I3C provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature or those in the spec. When we combine that with the ability of the testsuite to reach nearly every vPlan item, we verify the design effectively, easily, and methodically. In addition, using the TripleCheck IP Validator for MIPI I3C helps the team to assess the project's progress by tracking the overall coverage grade week by week. The vPlan can be filtered based on the specified configuration, which holds a set of parameters describing the DUT. A user can match the vPlan sections to the design under test (DUT) capabilities, thus allowing the vPlan to automatically filter out portions of the specification that are irrelevant to a particular design.
For some, it is important to reuse parts from an old environment. The vPlan's design allows users to incorporate the provided vPlan with the user's own vPlans. Moreover, the coverage model is not connected in any way to the testsuite, which means you can always run the legacy tests and collect coverage from those runs.
The combination of visualization that the TripleCheck IP Validator for MIPI I3C allows and the industry-proven VIP for I3C offers a complete solution for teams where time is is critical.
The TripleCheck IP Validator for MIPI I3C supports the MIPI I3C specification version 1.0 and the I2C specification.
The MIPI I3C specifications are accessible to registered users at www.mipi.org.
For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.
TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.
Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions.
TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.
The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.
In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.
PCI Express Features
Advanced Error Reporting
Stimuli and coverage collection of all applicable error scenarios
|Full LTSSM Transitions||Stimuli and coverage collection of all LTSSM transitions|
|Equalization Procedure||Stimuli and coverage collection of all aspects of equalization process|
|Packet Formation Rules||Stimuli and coverage collection of all applicable TLPs|
TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.
|Constrained-random example tests|
|Directed compliance tests|
|Constrained-random compliance tests|
|Tests targeting all protocol layers|
|3rd party simulator test execution|
|SystemVerilog functional coverage model|
|efunctional coverage model|
|Verification plan mapped to protocol specification|
|Verification plan integration with Cadence vManager metric-driven analysis system|
|Verification plan integration with 3rd party simulator environments|