The Cadence® TripleCheck Verification IP (VIP) for MIPI® DSI-2sm adds another layer of verification capability above the VIP for MIPI Display Serial Interface 2 (includes C-PHY, D-PHY, DBI, and DPI) for DSI-2 peripheral. The TripleCheck VIP for DSI-2 lays its foundations on three main components:
The vPlan was built in accordance with the specification structure and formations, using the same sections, headlines, and quotations from the spec. Overall, the vPlan contains over 70 specification quotations, each of which is related to a coverage item. The testsuite is designed for robustness and can run on any simulator with any testbench language to achieve the same result.
The TripleCheck VIP for DSI-2 provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature in the specification. When we combine that with the ability of the testsuite to reach nearly every vPlan item, we verify the design effectively, easily, and methodically. In addition, using TripleCheck helps the team to assess progress of the project by tracking the overall coverage grade week by week. The vPlan can be filtered based on the specified configuration, which holds a set of parameters describing the DUT. You can match the vPlan sections to the DUT capabilities, thus allowing the vPlan to automatically filter portions of the specification that are irrelevant to a particular design.
For some, it is important to reuse parts from an old environment. The design of the vPlan allows you to incorporate the provided vPlan with your existing vPlans. Moreover, the coverage model is not connected to the testsuite, which means you can always run the legacy tests and collect coverage.
The combination of visualization that TripleCheck allows and the industry-proven VIP for DSI-2 offers a complete solution for teams where time is critical.
The TripleCheck VIP for DSI-2 supports the MIPI DSI-2 specifications developed and maintained by MIPI, which are accessible to registered users at http://www.mipi.org.
The TripleCheck VIP for DSI-2 now supports the latest MIPI DSI-2 Peripheral Conformance Test Suite:
Key features from the specification that are implemented in the VIP are listed in the following table:
|Transaction Formation Rules|
|Multi-Lane Distribution and Merging||
|Low-Level Protocol (DSI-2 frames and packet structures)|
|Low-Level Error Detection and Contention|
|D-PHY/C-PHY Error Scenarios|
|Power State (HS-LS Data Transmission)|
LP Capabilities (ULPM, LP, trigger data transfer)
TripleCheck VIP for DSI-2 :
TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.
TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.
Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions.
TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.
The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.
In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.
MIPI CSI-2 Features
Key features from the spec that are implemented in the VIP are listed in the following table:
|Advanced error reporting||
Stimulus and coverage collection for all applicable error scenarios.
|State machines||Stimulus and coverage collection for all state machine transitions.|
|Transaction formation rules||Stimulus and coverage collection for all applicable transactions.|
|Physical layer||4 MIPI D-PHYsm or C-PHYsm data lanes for the CSI-2 receiver DUT.|
|Multi lane distribution and merging||Distribution and merging of data between data lanes.|
|Low level protocol||CSI-2 frames and packet structures.|
|Data Formats||All valid CSI-2 data types.|
|Annex C - CSI-2 recommended receiver error behavior||Error scenarios in the D-PHY, packet, and frame layers.|
|C-PHY errors||Multiple error scenarios for C-PHY physical layer.|
|MIPI CSI-2 Receiver Protocol Conformance Test Suite||The TripleCheck test suite includes the implementation of all CTS tests that are defined in CSI-2 Receiver Protocol Conformance Test Suite Version 1.01.|
|D-PHY v1.2 features||The suite supports the D-PHY 1.2 skew calibration feature (Initial and Periodic) + low-power data after triggers.|
|Physical layer||Support C-PHY and D-PHY PPI interface for both master and slave configurations.|
|UVM config suport||Supports UVM config environments for all TripleCheck flavors.|
TripleCheck VIP for CSI-2:
TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.
|Constrained-random example tests|
|Directed compliance tests|
|Constrained-random compliance tests|
|Tests targeting all protocol layers|
|3rd party simulator test execution|
|SystemVerilog functional coverage model|
|efunctional coverage model|
|Verification plan mapped to protocol specification|
|Verification plan integration with Cadence vManager metric-driven analysis system|
|Verification plan integration with 3rd party simulator environments|