Home: IP Portfolio > Verification IP > Productivity Tools

Productivity Tools

Boost Productivity with Products that Complement Our VIP

System-on-chip (SoC) verification is a big job. That's why high-level verification languages like e and SystemVerilog were developed along with companion methodologies like the Universal Verification Methodology (UVM). But language and methodology only take you so far.

Cadence provides additional productivity-boosting tools to help you configure, run, and analyze your design. With these products, you get up and running quickly and shorten your overall verification project.

Indago Protocol Debug App

View Demo

 

Product Description

Verifying the standard interfaces in IP blocks and SoCs can be one of the most resource-intensive tasks for verification teams. Popular interface specification families such as ARM® AMBA®, DDR, MIPI, PCIe Express, USB and others have undergone major expansions in recent years. Verification engineers seldom have more than a couple weeks to ramp up on a new protocol before they have to start verifying designs incorporating it. Commercial VIP helps offload part of the verification effort, but engineers still need a window into the protocol-specific interactions between the design, the VIP, and the testbench to find the root causes of bugs. Such a window is provided by the Indago Protocol Debug App, which presents a holistic picture of the verification environment in four views.

Key Features

  • Visualization of data and control traffic in protocol terminology

  • Ability to go back and forth in simulation time
  • All debug information automatically collected from Verification IP

  • View of complete testbench with multiple protocols/ instances

  • Synchronized view of messages, state machines, parameters and data traffic

  • Supports all simulators

Channel Viewer

  • Graphical presentation of transactions clarifies design behavior
  • Select data types or packets to see preferred level of detail
  • Error highlighting reveals design bugs
  • Highlights connection between different transactions

State Machine Viewer

  • State machine diagrams relate design behavior to specification terminology
  • See what states were visited during simulation
  • View reasons for state changes and see event timing
  • Drill down to lower-level state machines

Smart Log

  • Simple, intuitive way to filter the log file to your specific needs

  • Set up multi-level queries to save and share

  • Warnings and errors highlighted and connected to relevant packets

Life Story

  • See everything that happened to a given object during simulation
  • View registers, packets, state machines, lanes, queues configuration space, etc.
  • Filter history to focus on important events
  • Merge object histories from multiple simulations

Hierarchy Viewer

  • Lists the VIP instances of the recorded simulation for multiple protocols

  • Displays the values of VIP attributes of each instance such as Configuration, Call backs, Registers, Internal queues, Interesting events

  • Acts as a starting point in the simulation analysis 

  • Enables opening the more specific viewers – such as channel, memory, and FSM – per instance

The Channel Viewer portrays the communication between the design and VIP with a lab equipment-style view showing the sequence of transactions with protocol-specific labeling. The State Machine Viewer shows a graphical view of the state machines within the VIP components along with the causes of state transitions. The Life Story and Smart Log provide detailed views of all events pertaining to simulation objects and smart filtering of messages. Together, these views present an integrated picture of the design and verification environment to simplify the debugging process.

PureView

PureView is a graphical cockpit used to configure all our VIP products. Many interface protocols have dozens of configuration options. To match a VIP component to your design, each option needs to be set correctly. It would be time-consuming and error-prone to set every parameter with a text command, but PureView makes it easy.  The tool walks you through a hierarchy of menus to configure a VIP component. It only shows you relevant options based on previous choices and prevents illegal settings. PureView is also used to configure memory model options and TripleCheck tests.

Example PureView menus for PCI Express VIP configuration

TripleCheck for MIPI UniPro 1.6

TripleCheck for MIPI UniPro 1.6 helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. 

PureView Integration

TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

MIPI UniPro Features

Feature Name
Description

Advanced error reporting

Stimuli and coverage collection of all applicable error scenarios

State machines Stimuli and coverage collection of all state machine transitions
Transaction formation rules Stimuli and coverage collection of all applicable transactions

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution.  It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck for PCI Express

TripleCheck for PCI Express helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters.  TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan. 

PureView Integration

For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

PCI Express Features

Feature Name
Description

Advanced Error Reporting

Stimuli and coverage collection of all applicable error scenarios

Full LTSSM Transitions Stimuli and coverage collection of all LTSSM transitions
Equalization Procedure Stimuli and coverage collection of all aspects of equalization process
Packet Formation Rules Stimuli and coverage collection of all applicable TLPs

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck for MIPI CSI-2

The Cadence® TripleCheck Verification IP (VIP) for MIPI® CSI-2sm adds another layer of verification capabilities above the VIP for MIPI Camera Serial Interface (includes D-PHY) . The TripleCheck VIP for CSI-2 lays its foundations upon three main components:

  • The coverage model of the basic VIP
  • A comprehensive pre-packaged test suite
  • Verification plan (vPlan) constructed to match the spec format

The vPlan was built in accordance with the spec structure and formations, using the same sections, headlines, and quotations from the spec. Overall, the vPlan contains over 70 spec quotations, each of which is related to a coverage item. The testsuite is designed for robustness and can run on any simulator with any testbench language to achieve the same result.

The TripleCheck VIP for CSI-2 provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature in the spec. When we combine that with the ability of the testsuite to reach nearly every vPlan item, we verify the design effectively, easily, and methodically. In addition, using TripleCheck helps the team to assess the project's progress by tracking the overall coverage grade week by week. The vPlan can be filtered based on the specified configuration which holds a set of parameters describing the DUT. A user can match the VPlan sections to the DUT capabilities, thus allowing the vPlan to automatically filter portions of the spec that are irrelevant to a particular design.

For some, it is important to reuse parts from an old environment. The vPlan's design allows users to incorporate the provided vPlan with the user's own vPlans. Moreover, the coverage model is not connected in any way to the testsuite, which means you can always run the legacy tests and collect coverage from those runs.

The combination of visualization that TripleCheck allows and the industry-proven VIP for CSI-2 offer a complete solution for teams where time is of the essence.

Specification Support

The TripleCheck VIP for CSI-2 supports the MIPI CSI-2 Receiver specifications developed and maintained by MIPI, which are accessible to registered users at:  http://www.mipi.org.

The TripleCheck VIP for CSI-2 now supports the latest MIPI CSI-2 receiver Conformance Test Suite:

PureView Integration

For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

MIPI CSI-2 Features

Key features from the spec that are implemented in the VIP are listed in the following table:

Feature Name
Vplan
Coverage

Test Suite

State machines (tick) (tick) (tick)
Transaction formation rules (tick) (tick) (tick)
Physical layer (tick) (tick) (tick)
Multi lane distribution and merging (tick)

(tick)

(tick)
Low level protocol (tick) (tick) (tick)
Data Formats (tick) (tick) (tick)
Annex C - CSI-2 recommended receiver error behavior   (tick) (tick)
C-PHY errors (tick) (tick) (tick)
MIPI CSI-2 Receiver Protocol Conformance Test Suite   (tick) (tick)
C-PHY v1.2 features   (tick) (tick)
D-PHY v1.2 features   (tick) (tick)
Physical layer (tick) (tick) (tick)
D-PHY v2.1 features   (tick) (tick)
CSI2 v2.0 features

(tick)

(tick)

(tick)

 Key Verification Capabilities

TripleCheck VIP for CSI-2:

  • Runs on IES and VCS.
  • Supports SystemVerilog UVM.
  • Maps each vPlan item to a specific coverage group.
  • vPlan for the different clauses separately.
  • Is easily extended to reuse existing vPlans.

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution.  It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck for MIPI DSI-2

The Cadence® TripleCheck Verification IP (VIP) for MIPI® DSI-2sm adds another layer of verification capability above the VIP for MIPI Display Serial Interface 2 (includes C-PHY, D-PHY, DBI, and DPI) for DSI-2 peripheral. The TripleCheck VIP for DSI-2 lays its foundations on three main components:

  • The coverage model of the basic VIP
  • A comprehensive pre-packaged test suite
  • A verification plan (vPlan) constructed to match the specification format

The vPlan was built in accordance with the specification structure and formations, using the same sections, headlines, and quotations from the spec. Overall, the vPlan contains over 70 specification quotations, each of which is related to a coverage item. The testsuite is designed for robustness and can run on any simulator with any testbench language to achieve the same result.

The TripleCheck VIP for DSI-2 provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature in the specification. When we combine that with the ability of the testsuite to reach nearly every vPlan item, we verify the design effectively, easily, and methodically. In addition, using TripleCheck helps the team to assess progress of the project by tracking the overall coverage grade week by week. The vPlan can be filtered based on the specified configuration, which holds a set of parameters describing the DUT. You can match the vPlan sections to the DUT capabilities, thus allowing the vPlan to automatically filter portions of the specification that are irrelevant to a particular design.

For some, it is important to reuse parts from an old environment. The design of the vPlan allows you to incorporate the provided vPlan with your existing vPlans. Moreover, the coverage model is not connected to the testsuite, which means you can always run the legacy tests and collect coverage.

The combination of visualization that TripleCheck allows and the industry-proven VIP for DSI-2 offers a complete solution for teams where time is critical.

Specification Support

The TripleCheck VIP for DSI-2 supports the MIPI DSI-2 specifications developed and maintained by MIPI, which are accessible to registered users at http://www.mipi.org.

The TripleCheck VIP for DSI-2 now supports the latest MIPI DSI-2 Peripheral Conformance Test Suite:

PureView Integration

For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

MIPI DSI-2 Features

Key features from the specification that are implemented in the VIP are listed in the following table:

Feature Name
vPlan
Coverage

Test Suite

State Machine (tick) (tick) (tick)
Transaction Formation Rules (tick) (tick) (tick)
Physical Layer (tick) (tick) (tick)
Multi-Lane Distribution and Merging (tick)

(tick)

(tick)
Low-Level Protocol (DSI-2 frames and packet structures) (tick) (tick) (tick)
Data Formats (tick) (tick) (tick)
Low-Level Error Detection and Contention (tick) (tick) (tick)
D-PHY/C-PHY Error Scenarios (tick) (tick) (tick)
Power State (HS-LS Data Transmission) (tick) (tick) (tick)

LP Capabilities (ULPM, LP, trigger data transfer)

(tick) (tick) (tick)

Key Verification Capabilities

TripleCheck VIP for DSI-2 :

  • Runs on IES and VCS
  • Supports SystemVerilog UVM
  • Maps each vPlan item to a specific coverage group
  • vPlan for the different clauses separately
  • Is easily extended to reuse existing vPlans

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck for MIPI I3C

The Cadence® TripleCheck IP Validator for MIPI® I3C adds another layer of verification capabilities above the VIP for MIPI I3C for I3C slave devices. The TripleCheck IP Validator for MIPI I3C lays its foundation on the three main components:

  • The coverage model of the basic VIP
  • A comprehensive pre-packaged test suite
  • Verification plan (vPlan) constructed to match the specification format

The vPlan was built in accordance to the specification structure and formations, using the same sections, headlines, and quotations from the specification. Overall, the vPlan contains specification quotations, each of which is related to a coverage item. The testsuite is designed for robustness and can run on any simulator with any testbench language to achieve the same result—at least 95% overall coverage score in our vPlan.

The TripleCheck IP Validator for MIPI I3C provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature or those in the spec. When we combine that with the ability of the testsuite to reach nearly every vPlan item, we verify the design effectively, easily, and methodically. In addition, using the TripleCheck IP Validator for MIPI I3C helps the team to assess the project's progress by tracking the overall coverage grade week by week. The vPlan can be filtered based on the specified configuration, which holds a set of parameters describing the DUT. A user can match the vPlan sections to the design under test (DUT) capabilities, thus allowing the vPlan to automatically filter out portions of the specification that are irrelevant to a particular design.

For some, it is important to reuse parts from an old environment. The vPlan's design allows users to incorporate the provided vPlan with the user's own vPlans. Moreover, the coverage model is not connected in any way to the testsuite, which means you can always run the legacy tests and collect coverage from those runs.

The combination of visualization that the TripleCheck IP Validator for MIPI I3C allows and the industry-proven VIP for I3C offers a complete solution for teams where time is is critical.

Specification Support

The TripleCheck IP Validator for MIPI I3C supports the MIPI I3C specification version 1.0 and the I2C specification.

The MIPI I3C specifications are accessible to registered users at www.mipi.org.

PureView Integration

For quick set-up, TripleCheck is integrated with our PureView solution. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

PCI Express Features

Feature Name
Description

Advanced Error Reporting

Stimuli and coverage collection of all applicable error scenarios

Full LTSSM Transitions Stimuli and coverage collection of all LTSSM transitions
Equalization Procedure Stimuli and coverage collection of all aspects of equalization process
Packet Formation Rules Stimuli and coverage collection of all applicable TLPs

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution. It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck for MIPI SoundWire

TripleCheck for MIPI Soundwire helps you verify that your design complies with the interface specification. This is different than a post-silicon compliance test that measures electrical parameters. TripleCheck works during pre-silicon logic simulation to stress-test functional behavior. TripleCheck is the third-generation compliance product to be offered by Cadence, delivering an enhanced test suite, coverage model, and verification plan.

PureView Integration

TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

MIPI SoundWire Features

Feature Name
Multi-Lane Payload Transport
High-PHY Mode
Synchronization
Enumeration
Data payload traffic
Bank switching
Resets
Error scenarios
Interrupts
Multicast and broadcast slave accesses
Test data modes
Slave command responses
Command ownership
Flow control
Bulk Payload

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution.  It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

TripleCheck IP Validator for DisplayPort

The Cadence® TripleCheck IP Validator for DisplayPort product provides advanced verification capabilities suite in conjunction with the Cadence Verification IP (VIP) for DisplayPort. It is a product used for ensuring the compliance of the DUT to the DisplayPort specifications through a combination of the following main components :

  • The coverage model of the basic VIP
  • A comprehensive pre-packaged testsuite
  • Verification plans (vPlans) constructed to match the specification format

Product Description

Track the progress

The Cadence TripleCheck IP Validator for DisplayPort provides an easier way to ramp up quickly on your verification tasks. The vPlan helps to focus on a specific feature or those in the specification. When we combine that with the ability of the testsuite to reach every vPlan item, we ensure that the design works in compliance with the specifications, easily and methodically. In addition, by using a TripleCheck vPlan, the team can assess the project's progress by simply tracking the overall coverage grade week by week.

See only what you need

The vPlans are built in accordance to the specification document structure, using the same sections and titles from the specification so that it is easier to check corresponding sections and annotations. The vPlan consists of "perspectives"—views of the vPlan that can be customized according to the DUT behavior using a set of parameters that roughly describe the DUT. A user is able to edit the perspective to match the DUT capabilities that allow the vPlan to automatically filter out portions of the specification that are irrelevant for a particular design.

Reuse the existing test coverage

In case there is a significant chunk of legacy tests, verification engineers can leverage the coverage from this library of tests as well. The vPlan allows users to incorporate the TripleCheck-provided vPlan with the user's own vPlans. Moreover, the cumulative coverage from these tests as well as TripleCheck testsuite can be plotted on the same vPlan to enhance the reach of the solution according to customer needs.

Testsuite

Currently, the TripleCheck solution contains over 250 self-checking tests in the testsuite based on VESA Compliance specification for DisplayPort and HDCP.

  • These tests are mapped to vPlan sections through relevant coverage items
  • Robust testsuite able to run on major simulators
  • Most of the testcases are directed with consistency in results across simulators and seeds
  • Testcase description present in the test list as well as documented with step-by-step guidance for understanding the purpose and behavior of the tests

The thorough testsuite, elaborated coverage model, and the vPlan visualization to track verification progress combined with the industry proven VIP for DisplayPort core offer a complete and monolithic solution for verification teams working on VIP for DisplayPort with consistent results when time to market is of essence.

Specification

DisplayPort TripleCheck supports :
  • VESA DisplayPort Link Layer Compliance Test Specification, Revision 1.0, October, 2016
  • HDCP Interface Independent Adaptation, Revision 2.2, Compliance Test Specification, Version 1.1, January, 2014
  • DisplayPort-HDCP Specification Compliance Test Specification Revision 1.0, September, 2007
The specification can be downloaded from the website at http://www.vesa.org.

 

Product Features

Key features from the specification that are implemented in the VIP are listed in the table below.  

FEATURE NAME

vPLAN COVERAGE TEST SUITE

Source/Sink Link Training

(tick) (tick) (tick)

Source/Sink Link Maintenance

(tick) (tick) (tick)

Source/Sink AUX Services

(tick) (tick) (tick)

DPCD Operations/Control

(tick) (tick) (tick)

DP Video Transmission

(tick) (tick) (tick)

Power Management

(tick) (tick) (tick)

High Bit Rate (HBR3)

(tick) (tick) (tick)

IRQ HPD Operation

(tick) (tick) (tick)

HDCP 1.3 TX/RX w/o Repeater

(tick) (tick) (tick)

HDCP 2.2 TX/RX w/o Repeater

(tick) (tick) (tick)

Key Verification Capabilities

TripleCheck IP Validator for DisplayPort:

  • Comprehensive testsuite with 250+ self-checking tests
  • Supports SystemVerilog UVM
  • Runs on IES and VCS
  • Its vPlan includes mapping of VESA DisplayPort Link Layer Compliance Test Specification Revision 1.0, and HDCP Interface Independent Adaptation, Revision 2.2, Compliance Test Specification, Version 1.1
  • Maps each vPlan item to a specific test designed to stimulate that feature
  • Is easily extended to reuse existing vPlans
  • Can initiate stimulus from the DUT using the Port Driver

 

PureView Integration

TripleCheck is integrated with our PureView solution for quick set-up. When you configure a VIP with PureView, the TripleCheck test suite, coverage model, and vPlan are automatically configured to match the VIP.

Test Suite

TripleCheck provides an extensive library of test sequences to stimulate the design under test. The test library contains directed tests (providing quick checks for common protocol compliance issues) as well as constrained-random test sequences for exhaustive testing to detect corner-case bugs hidden in the design. The tests support error injection in each layer of the protocol stack to check operation of the design when faced with non-compliant stimulus. This combination of directed and constrained-random tests results in high functional coverage, right out of the box.

Coverage Model

Coverage models are provided in both SystemVerilog and e verification languages. These pre-defined coverage models capture all data items and state machine transitions to track and measure verification progress. The coverage models are open and documented, which allows you to extend them with application-specific coverage definitions. 

Verification Plan

TripleCheck provides a verification plan that mirrors the protocol specification. All the requirements in the protocol specification are listed in the plan and organized into the same chapter and paragraph hierarchy.

The vPlan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped against the plan. This makes it easy to track verification progress and determine how much work remains. The vPlan is written in XML to enable portability between simulation environments.

In the Xcelium™ simulation environment, TripleCheck integrates with the vManagert tool to enable a number of productivity-boosting features, such as bucket analysis to analyze coverage details and test profiling to sort out unproductive test sequences.

MIPI CSI-2 Features

Key features from the spec that are implemented in the VIP are listed in the following table:

Feature Name
Description
Advanced error reporting

Stimulus and coverage collection for all applicable error scenarios.

State machines Stimulus and coverage collection for all state machine transitions.
Transaction formation rules Stimulus and coverage collection for all applicable transactions.
Physical layer 4 MIPI D-PHYsm or C-PHYsm data lanes for the CSI-2 receiver DUT.
Multi lane distribution and merging Distribution and merging of data between data lanes.
Low level protocol CSI-2 frames and packet structures.
Data Formats All valid CSI-2 data types.
Annex C - CSI-2 recommended receiver error behavior Error scenarios in the D-PHY, packet, and frame layers.
C-PHY errors Multiple error scenarios for C-PHY physical layer.
MIPI CSI-2 Receiver Protocol Conformance Test Suite The TripleCheck test suite includes the implementation of all CTS tests that are defined in CSI-2 Receiver Protocol Conformance Test Suite Version 1.01.
D-PHY v1.2 features The suite supports the D-PHY 1.2 skew calibration feature (Initial and Periodic) + low-power data after triggers.
Physical layer Support C-PHY and D-PHY PPI interface for both master and slave configurations.
UVM config suport Supports UVM config environments for all TripleCheck flavors.

Key Verification Capabilities

TripleCheck VIP for CSI-2:

  • Runs on IES and VCS.
  • Supports SystemVerilog UVM.
  • Maps each vPlan item to a specific coverage group.
  • vPlan for the different clauses separately.
  • Is easily extended to reuse existing vPlans.

Third-Generation Solution

TripleCheck is a third-generation pre-silicon compliance test suite solution.  It combines the features from Cadence's other test suite solutions to deliver the most advanced pre-silicon compliance test suite on the market.

Test Suite Comparison

 BasicCMSPureSuiteTripleCheck
Constrained-random example tests
Directed compliance tests
Constrained-random compliance tests
Tests targeting all protocol layers
3rd party simulator test execution
SystemVerilog functional coverage model
efunctional coverage model
Verification plan mapped to protocol specification
Verification plan integration with Cadence vManager metric-driven analysis system
Verification plan integration with 3rd party simulator environments

 

VIP for USB 3.0 PureSuite

The Cadence® Verification IP (VIP) for USB 3.0 PureSuite provides a pre-built USB 3.0 compliance test suite. It complements the Cadence VIP for USB 3.0 by providing test sequences, test plan, and functional coverage that makes verification easier and faster.

The VIP for USB 3.0 PureSuite provides support to verify the USB 3.0 Device or Host or PHY. It also provides test sequences to test backward compatibility with USB 2.0 and some USB 2.0 sequences as well. It is based upon System Verilog, available for both OVM and UVM, and runs on all leading simulators.

 

Specification

The base specification for the USB 3.0 protocol is available at http://www.usb.org/developers/docs.

Features

Feature Name
Description

Test Sequences

A library of sequences and test scenarios generate constrained-random stimulus to target all aspects of the USB specification.

Test Plan

The included test plan is based on the USB specification and covers all useful spec-defined cover points.

Functional Coverage

A complete set of coverage points to cover the USB specification and all layers is defined.

Key Verification Capabilities

  • The user is able to further customize the sequence library by adding additional constraints to currently available sequences, or by adding additional sequences to the library

  • The test sequences cover all the layers of the USB protocol

  • The test plan is available for all leading simulators and can be easily back annotated with the functional coverage collected at the end of the simulation runs

  • Methodology support: Complies with the Universal Verification Methodology (UVM) and OVM

  • Simulator support: IES, VCS, MTI

 Other Supported Features

Testbench Language Interfaces SystemVerilog
UVM Agent Yes
Trace Debug Yes
Assertion Coverage Yes
Functional Coverage - SV Yes
Compliance Management System _
TripleCheck

Training