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Wide I/O 2

Specification Support

The Wide I/O 2 DDRAM Memory Model VIP supports single-channel implementation  version of the Wide I/O 2 DDR specification (the final specs have not yet been released by JEDEC), and can be used 4 times to model a single slice (4-channel device), or 8 times to model a 2-slice (8-channel) device.

Key Features

Feature Name
Test Feature Support for Boundary Scan, GPIO, and Post Package Repair
State machine and timing checks Implements internal Wide I/O 2 state machine and performs specified timing checks.

Data width

64-bit wide data bus. Double data rate.

Device density support The model supports a wide range of device densities.
Differential DQS Complimentary data strobe for every 16 data bits.


  • Partial-array self refresh 
  • Per-bank refresh
Allows portions of the array to be powered down when not required, permitting applications to determine device memory requirements on a real-time usage basis.