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VIP for DFI

VIP for DFI

The Cadence® Verification IP (VIP) for DFI provides a mature, highly capable compliance verification solution for the DFI protocol. The VIP supports the simulation platform and enables metric-driven verification of IP and system-on-chip (SoC) designs against DFI protocol specifications. DFI VIP supports both the Memory Controller (MC) traffic generation and the PHY component, which samples from the DFI interface and drives to the memory interface for different memory variants. DFI VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Specification Support

DDR_PHY_Interface_Specification_v4_0
DDR_PHY_Interface_Specification_v5_0

DFI MC Features

The following table describes key features from the specification for the simulated DFI MC that are implemented in the VIP.

Feature Name
Description
Supported Memory

Command Interface

Drives Command on different phases based on memory protocol requirement

DDR4-5, LPDDR4-5, and HBM

Command to Command Delay

Configurable different timing constraint requirements while driving a command through DFI interface for the memory

DDR4-5, LPDDR4-5, and HBM

Data Interface

Read and Write Data Interface

DDR4-5, LPDDR4-5, and HBM

Update Interface

MC-initiated and PHY initiated updates

DDR4-5, LPDDR4-5, and HBM

Training Interface

CA, Write, Write DQ, Read Training (both MC initiated and PHY initiated)

DDR4, LPDDR4

PHY Master Interface

Support for PHY Master Interface

DDR4-5, LPDDR4-5, and HBM

WCK Interface

Support for WCK Interface

LPDDR5

Frequency Change Protocol

Initiates frequency change

DDR4-5, LPDDR4-5, and HBM

Low Power Control

Initiates Low-Power Entry as per DFI5.0 and DFI4.0

DDR4-5, LPDDR4-5, and HBM

Data CS Gap

Data Path Chip Select Gap (Per Rank Delay line support)

DDR4-5, LPDDR4-5, and HBM

Refresh Command

Sends Refresh All and Refresh Per Bank command on every internal

 DDR4-5, LPDDR4-5, AND HBM

DFI Interactions

DFI Interaction rules as per DFI 5.0

DDR5 and LPDDR5

2N Mode

Command transmission in 2N Mode

DDR5

DBI and Data Mask

Generates Inverted/Masked Write Data and Invert received Read Data with dfi_rddata_dbi enabled

DDR4-5, LPDDR4-5, and HBM

CRC

Generates CRC and Error injection

DDR5

Frequency Ratio

All possible frequency ratios as per specification

DDR4-5, LPDDR4-5, and HBM

GearDown Mode

Command transmission in GearDown Mode

DDR4

Checkers

Perform timing and protocol checks for signals driven by PHY

DDR4-5, LPDDR4-5, and HBM

Multi Channel Mode

Configurable Single/Multiple (Independent/Combine) Channel Interface

LPDDR4 and HBM

DFI PHY Features

The following table describes key features from the specification for the simulated PHY side that are implemented in the VIP.

Feature Name
Description
Supported Memory

Command Interface

Drives Command on different phases based on memory protocol requirement

LPDDR4-5, DDR5

Data Interface

Read and Write Data Interface

LPDDR4-5, DDR5

Update Interface

MC-initiated and PHY initiated updates

LPDDR4-5, DDR5

PHY Master Interface

Support for PHY Master Interface

LPDDR4-5, DDR5

WCK Interface

Support for WCK Interface

LPDDR5

Frequency Change Protocol

Initiates frequency change

LPDDR4-5, DDR5

Low Power Control

Initiates Low-Power Entry as per DFI5.0 and DFI4.0

LPDDR4-5, DDR5

Data CS Gap

Data Path Chip Select Gap (Per Rank Delay line support)

LPDDR5, DDR5

DFI Interactions

DFI Interaction rules as per DFI 5.0

LPDDR5,DDR5

DBI and Data Mask

Generates Inverted/Masked Write Data and Invert received Read Data with dfi_rddata_dbi enabled

LPDDR4-5, DDR5

Frequency Ratio

All possible frequency ratios as per specification

LPDDR4-5, DDR5

DRAM Interface

Support DRAM interface as per required by DRAM

LPDDR4-5, DDR5

Initialization/PHY Training

Fully configurable Initialization training for memory model, also PHY can initiate training independently through registers

LPDDR4-5, DDR5

Run-time configurations

PHY decodes MRW/MPC commands and auto-update its configuration, read-write latency based on that

LPDDR4-5, DDR5

Multi Rank

Support Multi Rank transfer Interface

LPDDR4-5, DDR5

DBI

Generates Inverted Write Data and Invert received Read Data if DBI is enabled in PHY

LPDDR4-5

ECC

Generates ECC for Write Data and check ECC for received Read Data ECC is enabled in PHY

LPDDR5

WCK

Support Generation of WCK based on WCK:CK Ratio

LPDDR5

CK

Support Generation of DRAM Clock based on frequency Ratio

LPDDR4-5, DDR5

Training

Support all the training required for DRAM

LPDDR4-5, DDR5

CRC

Generation of CRC when PHY CRC Mode is on

DDR5

Dual Channel

Configurable Single/Dual (Independent/Combine) Channel Interface

LPDDR4

Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage

  • Callbacku-based error injection capability for creation of illegal stimulus from the VIP

  • Monitor agent with analysis ports, which can be used for score-boarding purpose

  • Transaction tracker: Configurable tracking of all the transactions on the channels

Other Supported Features

Testbench Language Interfaces

SytemVerilog

UVM Methodology

Up to Version 1.2

Trace Debug

Yes

Functional Coverage -SystemVerilog

Yes

TripleCheck

Yes

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