Home: IP Portfolio > Verification IP > Memory Models > TripleCheck IP Validator for DFMIC

TripleCheck IP Validator for DFIMC

The Cadence® TripleCheck IP Validator for DFIMC adds another layer of verification capability above the DDR PHY Interface Micro Controller (DFIMC). The TripleCheck for DFIMC lays its foundation on a comprehensive pre-packaged test suite and on the coverage model of the DFIMC VIP.

The TripleCheck for DFIMC provides an easier way to ramp up quickly on your verification tasks. In addition, using TripleCheck helps the team to assess the project's progress by tracking the overall coverage grade week by week. Tests can be filtered based on the specified configuration, which holds a set of parameters describing the DUT. The coverage model is not connected in any way to the test suite, which means you can always run the legacy tests and collect coverage from those runs.

The combination of visualization that TripleCheck allows and the industry-proven DFIMC VIP core offers a complete solution for teams where time is of great essence.

The TripleCheck for DFIMC covers the Memory Models DDR4, DDR5, LPDDR4, LPDDR5, HBM2E, and HBM3.

Specification Support

Protocol Features

Key features from the specification that are implemented in the VIP and covered by the TripleCheck are listed in the following table:

FEATURE NAME

vPLAN COVERAGE TEST SUITE

Command Interface

(tick) (tick)

Data Interface

(tick) (tick)

Update Interface

(tick) (tick)

Training Interface

(tick) (tick)

PHY Master Interface

(tick) (tick)

WCK Interface

(tick) (tick)

Frequency Change Protocol

(tick) (tick)

Low Power Control

(tick) (tick)

Refresh Command

(tick) (tick)

DFI Interactions

(tick) (tick)

DBI and Data Mask

(tick) (tick)

Frequency Ratio

(tick) (tick)

GearDown Mode/2 N Mode

(tick) (tick)

Key Verification Capabilities

  • Runs on IES and VCS
  • Supports SystemVerilog UVM based environment

Related Products