HyperRAM

The Cadence® Memory Model Verification IP (VIP) for HyperRAM provides verification of the HyperRAM controller using the Hyperbus as well as xSPI Interface protocol.

Specification Support

The model supports features of Cypress (Infineon) and Winbond. The specification is available from the vendor. 

The Cypress (Infineon) HyperRam device supports both interfaces: HyperBus as well as Octal Interface as HyperRam1.0 and HyperRam2.0 respectively.  

Key Features

The following table describes key features from the specification that are implemented in the Memory Model VIP for HyperRAM.

Feature Name

Description

Memory Operations

  • Memory Read and Write with Linear, Wrapped, and Hybrid Burst
  • Write Enable and Write Disable commands to enable WEL latch for xSPI Octal Interface Support - Cypress HyperRAM 2.0

Device Density

Supports device densities from 64Mb to 128Mb
Reset Functionality

Hardware Reset via RESET# pin

DCARS

DDR Center-Aligned Read Strobe Functionality for Cypress

Configurable Burst Characteristics

Supports three kinds of bursts:

  • Wrapped burst with lengths of 16, 32, 64, and 128 bytes
  • Linear burst
  • Hybrid burst: One wrapped burst followed by linear burst

Also supports wrapped or linear burst type selected in each transaction

Register Operations

Supports Read/Write operation for registers: ID0 and ID1 (Read Only) and CR0/1 (Read/Write)

For xSPI Octal Interface Support - Cypress HyperRAM 2.0:

  • Read and Write any register and Read ID
  • Select Burst type from CR1[7] bit
Timing Supports device input and output timing and variants memory operations timing
Extended I/O Support Winbond Specific: DQ[15:0] and RWDS[1:0]
Configuration Registers

Winbond Specific: Hybrid Sleep Mode, Partial Array Refresh, Master Clock Type, and Software Reset

Power Modes and Software Reset

For xSPI Octal Interface Support - Cypress HyperRAM 2.0: 

  • Deep Power Down
  • Software Reset: Reset, Reset Enable

 

Key verification Capabilities

  • Transaction callback events are available on requests and responses to monitor activity

  • Backdoor access: Allows backdoor Reads and Writes to volatile and non-volatile registers as well as device memory

  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker