HyperRAM

The Cadence® Memory Model Verification IP (VIP) for HyperRAM provides verification of HyperRAM controller using the HyperRAM protocol.

Specification Support

The model supports features of Cypress. The specification is available from the vendor. 

Early Adopter Program

The Early Adopter Program allows customers to gain early access to the Denali® Memory Model for HyperRAM, enabling the accelerated adoption of emerging memory protocols and, more importantly, to influence memory model product requirements to meet their project timelines by working closely with our architects and the broader Denali Memory Model team.  

For more information, please contact David Peña, Director of Product Strategy.

Product Highlights

  • Transaction callback events are available on requests and responses to monitor activity
  • Backdoor access: Allows backdoor Reads and Writes to volatile and non-volatile registers as well as device memory

Key Features

The following table describes key features from the specification that are implemented in the Memory Model for HyperRAM.

Feature Name
Description

Memory Read

Memory Read with Linear, Wrapped, and Hybrid Burst

Device Density

Supports device densities from 64Mb to 128Mb

Reset Functionality

Supports Reset functionality through

  • Hardware Reset (via RESET# pin)

DDR Center-Aligned Read Strobe Functionality (DCARS)

Supports phase shifting of the RWDS signal with respect to read data outputs using Phase Shifted Clock input PSC and PSC# pins.

Configurable Burst Characteristics

Supports three kinds of bursts:

  • Wrapped burst: Supports burst lengths of 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks), and 128 bytes (64 clocks)
  • Linear burst
  • Hybrid burst: One wrapped burst followed by linear burst

Also supports wrapped or linear burst type selected in each transaction

Register Read

 Supports Read operation for following Registers:

  • Identification Register 0 (ID0)
  • Identification Register 1 (ID1)
  • Configuration Register 0 (CR0)
  • Configuration Register 1 (CR1)

Timing

Supports Device Input and Output timing and Variants memory operations timing