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High-Bandwidth Memory (HBM)

This Cadence® Memory Model Verification IP (VIP) provides support for the JEDEC® High-Bandwidth Memory (HBM) DRAM device standard. It provides a mature, highly capable compliance-verification solution that supports simulation, formal-analysis, and hardware-acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for HBM models a single channel of HBM DRAM; this model can be replicated for multiple channels and multiple ranks. The Memory Model for HBM runs on all leading simulators and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The HBM DRAM standard is an industry-leading, low-power, double-data-rate, high-data-width, volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The HBM DRAM Memory Device Standard is designed to satisfy the performance and memory density demands of the leading-edge mobile devices. The Memory Model for HBM includes HBM legacy, HBM2, and HBM2E specifications.

Specification Support

The Memory Model for HBM supports single-channel implementation version of the HBM DRAM specification and can be used eight times to model a single 8-channel device.

JEDEC Standard

VIPCAT 11.3.057

JESD235B Rev 2.60 (HBM2E)

VIPCAT 11.3.051

JESD235B Rev 2.40 and 2.50

VIPCAT 11.3.045

JESD235B Rev 2.20

VIPCAT 11.3.038

JESD235B Rev 2.01

VIPCAT 11.3.031

JESD235 Rev 1.27

VIPCAT 11.3.033

JESD235 Rev 1.31

Product Highlights

  • Backdoor access: Allows backdoor reads and writes to mode registers as well as device memory
  • User ability to dynamically change timing parameter values or swap parts (SOMAs)
  • Callbacks: 
    • Memory and transaction callbacks for reads and writes; transaction callbacks for all other commands
    • Transaction protocol callbacks at command execution, data passed, and errors — for tie in to user's testbench scoreboard and reference model, with user ability to modify some fields to cause error injection (not in Verilog)
  • Comprehensive assertion library: Includes a large number of assertions for assertion coverage
  • Power-on initialization sequence can be optionally skipped to save simulation time
  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)
  • Refresh checks can be optionally skipped
  • Differential clock checks with configurable skew
  • UVM configuration: The user can configure the VIP agent using the UVM config class
  • IEEE 1500 and Loopback mode support

Key Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name

I/O Signals and Buses: data, control, address

All I/O signals including RD, RR, and RC are supported by HBM

Clocking and Reset

Differential clock inputs (CK_t/CK_c) and Active Low Reset Line (reset_n)

Command Decode

  • Reset
  • Mode Register Set
  • Precharge Same Bank 
  • Precharge All Bank
  • Refresh Single Bank
  • Refresh All Bank
  • Activate
  • Read
  • Read with Auto Precharge
  • Write
  • Write with Auto Precharge
  • Power Down Entry
  • Self Refresh Entry
  • Power Down/Self Refresh Exit

Speed (MHz)

1200MHz (2.4 Gbps/pin)

Initialization Sequence and Skip Initialization

Initialization sequence of HBM model is supported with all the timing checks (also IEEE 1500 Stable Power Initialization); this sequence can be skipped, too

Mode Registers

The command is used to load the Mode Registers of the HBM device and configured different functionality of HBM model

General HBM Functionality and Timing Checks

Precharge, Activate, Read, Write, Mode Register Set, Power Down, Self Refresh, Initialization, and all related timing checks

Support for 1GB, 2GB, and 4GB Legacy Modes

Size is programmable using SOMA; we model a single channel which can be replicated eight times to generate a 8-channel model

Support for Pseudo Channel Mode - 2GB, 4GB, 8GB

  • Size is programmable using SOMA; can model a single channel which can be replicated eight times to generate a 8-channel model
  • Divides a channel into two individual sub-channels of 64-bit I/O each


The stack ID (SID) acts as a bank address bit in command execution

Error-Correcting Code (ECC)

HBM DRAM devices support ECC (one bit per data byte); the HBM Model does not compute any ECC

ECC bits are not included in parity calculation when Write or Read DQ Parity Function is enabled

Data Mask and Data Bus Inversion

Data on the bus can be inverted during both read and write to save power; both Data Mask and Data Bus inversion features can be set through mode registers

C/A and Data Parity Check

  • Parity checking is off by default
  • When C/A parity is enabled, the parity is checked for each command before execution
  • When write parity is enabled, the parity is checked for each write data word (DQ, DM,DBI)
  • When read parity is enabled, the model generates parity signal for each read data word
  • Errors are reported through AERR and DERR signals

Targeted Row Refresh Mode

The TRR mode will refresh the rows adjacent to the TRn that encountered MAC(Maximum Activate Count) limit; there could be one or two target rows in a bank associated to one victim row

The cumulative value of the Activates from two target rows on a victim row should not exceed MAC value as well

Support for IEEE 1500/DFT Commands and Features

 HBM DFT support using IEEE 1500 interface features:

Loopback Test Mode Support

Register, LFSR, MISR, LFSR Compare (Sticky bit)

 HBM DFT support using Loopback mode feature

Soft Lane Repair and Hard Lane Repair

  • The HBM DRAM supports interconnect lane remapping to help recover functionality of the HBM stack
  • Lane remapping is independent for each channel
  • The HBM can be programmed to retain the remapped lane information even when power is completely removed from the HBM stack
  • Except CK_t, Ck_c , CKE and AERR, all other I/Os can be remapped using AWORD and DWORD Remapping

DWORD Repair Mode

HBM model supports two Repair Mode for DWORD remapping:

  • In Mode 1, it is allowed to remap one lane per byte; no redundant pin is allocated in this mode, and DBI functionality is lost for that byte only, however other bytes continue to support DBI function as long as the Mode Register setting for DBI function is enabled
  • In Mode 2, it is allowed to remap one lane per double byte; one redundant pin (RD) per double byte is allocated in this mode, and DBI functionality is preserved as long as the Mode Register setting for DBI function is enabled

RD, RC, and RR

HBM model support Redundant Row, Column values for AWORD Repair and Redundant Data(4 bits) value supported for DWORD Repair functionality

State Machine and Timing Checks

Implements internal HBM state machine and performs various command to command timing checks

Data Width

  • 128-bit wide data bus
  • Pseudo channel mode with 64-bit data per pseudo channel
  • DDR for Command and Data Phase

Device Density Support

The model supports a wide range of device densities from 1Gb to 32Gb

Differential ck, rdqs, and wdqs

  • Differential clock and data referenced to strobes RDQS_t/RDQS_c and WDQS_t/WDQS_c
  • 1 strobe pair per DWORD
  • Read and Write strobes for each pseudo channel are driven and read simultaneously

Bank Groups

Modeling the concept and the timing associated with back-to-back accesses to the same and different bank group


All bank, per-bank and self-refresh; refresh timing check; Normal mode refresh, Self refresh, Temperature controller self refresh supported

Cattrip and Temp Pin

HBM cattrip and Temp Pins functionality support for Temperature-controlled Refresh and Catastrophic Temperature Sensor

IEEE 1500 Functionality

Key features from the specification that are implemented in the VIP are shown below:

Feature Name

IEEE 1500 and Loopback

LFSR, AWORD and DWORD MISR, LFSR Compare (Sticky bit register); supports DFT and training

between the Host and HBM device

Port Modifications for HBM Specification


EXTEST_RX is intended for DC I/O connectivity testing similar to board level boundary scan; the receive notation designates that the HBM I/O will sample the logic value and capture into the data register the value that is present at the micro bump interface


EXTEST_TX is intended for DC I/O connectivity testing similar to board level boundary scan; the transmit notation designates that the HBM I/O will preload the logic value shifted into the data register at the micro bump interface

Mode Register Dump

This instruction provides IEEE Std 1500 access to read and write the HBM Mode Registers; when this instruction is updated into the WIR, the Mode Registers values are loaded into the MODE_REGISTER_ DUMP_SET WDR on Capture and the values in the shift data register are updated to the Mode Register upon update

Soft and Hard Lane Repair

The SOFT_LANE_REPAIR and HARD_LANE_REPAIR instructions are used to convey lane remapping and repair information; both instructions use the same LANE_REPAIR WDR

HBM Reset

The HBM_RESET instruction is intended to initiate an asynchronous functional reset of the HBM upon update, equivalent to assertion of RESET_n; MR registers and HBM functional logic is reset upon update of HBM_RESET instruction

Backdoor Access to all IEEE 1500 WDR Registers

HBM model supports backdoor access to all IEEE 1500 WDR registers

HBM2 Functionality

Key features from the specification that are implemented in the VIP are shown below:

Feature Name

Row and Column Width

Higher density HBM2E configuration supported by additional CA8 and RA6 Row and Column pins

Support for 8H and 12H Stack Configuration

Supports Pseudo Channel Mode 12H configuration - 12GB, 18GB, 24GB, Support for Pseudo Channel Mode 8H configuration - 8GB, 12GB, and 16GB

Mode Register

Supports Extended Read and Extended Write latency, and 34-bit AWORD polynomial for higher density HBM2 configuration

Command Decoding

All the Row and column command decoding are as per HBM2 configuration (with additional C8 and R6 pins)

Command and Address Parity

Command and Address parity calculations are as per the HBM2 configuration (with additional C8 and R6 pins)


BSCAN EXTEST_RX and EXTEST_TX commands accommodate CA8 and RA6 pads in AWORD (total WDR length changed from 215 to 217)

Soft and Hard Lane Repair

Soft and Hard Lane Repair command and register support CA8 and RA6 remapping


AWORD MISR Config WDR width support to match new length (length updated from 8 to 9)

AWORD MISR Polynomial

For higher density, HBM2 configurations that include the RA14 or SID1 address bit or both, AWORD implements both 30-bit and 34-bit MISR and LFSR circuit comprised of DDR Rise and Fall bits for the additional row and column command bits respectively, including CKE


MISR MASK WDR valid value changes for AWORD_RA_MASK[3:0] and AWORD_CA_MASK[3:0] for RA6 and CA8