GDDR6

This Cadence® Verification IP (VIP) provides support for the JEDEC® Graphics Double Data Rate (GDDR6) SGRAM GDDR6 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for GDDR6 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The GDDR6 standard is a modern type of synchronous graphics random-access memory (SGRAM) with a high-bandwidth ("double date rate") interface designed for use in graphics cards, game consoles, and high-performance computation.

Specification Support

The VIP for GDDR6 Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.

Key Features

Key features of the GDDR6 device standard supported by the Cadence GDDR6 VIP are listed below:

Feature Name
Description

Bank Architecture

16B and BankGroup supported.

General GDDR6 Functionality

Command decoding and related error conditions

Clock

  • CK (DDR)

  • WCK (DDR, QDR)

  • DFS (Clock frequency change)

Supported Commands

  • Refresh all banks (REFab)

  • Refresh per-bank (REFpb)

  • Refresh per-2 bank (REFp2b)

  • Activate (ACT)

  • Write without mask (WOM)

  • Write without mask with autoprecharge (WOMA)

  • Write with double-byte mask (WDM)

  • Write with double-byte mask with autoprecharge (WDMA)

  • Write with single-byte mask (WSM)

  • Write with single-byte mask with autoprecharge (WSMA)

  • Write Training (WRTR)

  • Read (RD)

  • Read with autoprecharge (RDA)

  • Read Training (RDTR)

  • Command Address Training Capture (CAT)

  • Precharge all banks (PREab)

  • Precharge per bank (PREpb)

  • Power down entry (PDE)

  • Power down exit (PDX)

  • Self refresh entry (SRE)

  • Self refresh exit (SRX)

  • No operation (NOP)

  • Mode Register Set (MRS)

Initialization

Power-up sequence, Stable Power Sequence

Interface Trainings

  • Command address training

  • WCK2CK training

  • Read training

  • Write training

Mode Registers

Supports register functionality for Low Power modes

Command Address Bus Inversion (CABI)

The number of CA lines driving a LOW level can be limited to 5 in 2-channel mode or 7 in PC mode for 8Gb, 12Gb and 16Gb densities and limited to 6 in 2-channel mode or 8 in PC mode for 24Gb and 32Gb densities

Data Bus Inversion (DBI)

  • Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register

Device Density

Supports a wide range of device densities from 8Gb to 32Gb

Error Detection Code (EDC)

Supports Error Detection Code hold pattern, CRC and special EDC in other states

Tccd Reads and Writes

Supports all combinations of Reads and Writes placed Tccd apart

Speed

Supports up to 16Gbps with current vendor datasheets

Key Verification Capabilities

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory

  • Ability to dynamically change the timing parameter

  • Ability to check for errors and change error severity

  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)

  • Registers to indicate the channel state, bank state, and initialization state

  • Initialization can be optionally skipped

  • UVM Configuration: Users can configure the VIP agent using the UVM config class

  • Functional coverage