This Cadence® Memory Model Verification IP (VIP) provides support for the JEDEC® Graphics Double Data Rate (GDDR6) SGRAM GDDR6 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for GDDR6 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

The GDDR6 standard is a modern type of synchronous graphics random-access memory (SGRAM) with a high-bandwidth ("double date rate") interface designed for use in graphics cards, game consoles, and high-performance computation.

Specification Support

The Memory Model for GDDR6 is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at

Early Adopter Program

The Early Adopter Program allows customers to gain early access to the Denali® Memory Model for GDDR6, enabling the accelerated adoption of emerging memory protocols and, more importantly, to influence memory model product requirements to meet their project timelines by working closely with our architects and the broader Denali Memory Model team.  

For more information, please contact David Peña, Director of Product Strategy.

Product Highlights

  • Transaction callback events on requests and responses to monitor activity
  • Backdoor access: Allows backdoor Reads and Writes to Volatile/Nonvolatile registers (Configuration and Security) as well as device memory
  • Error Injection support for ECC
  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Ability to dynamically change the timing parameter
  • Ability to check for errors and change error severity
  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)
  • Registers to indicate the model state, bank state, and initialization state
  • Initialization can be optionally skipped
  • UVM Configuration: Users can configure the VIP agent using the UVM config class
  • Functional coverage 

Key Features

Key features of the GDDR6 device standard supported by the VIP are listed below.

Feature Name
Bank Architecture 8B, 16B, and 2BankGroup supported
General GDDR6 Functionality Command decoding and related error conditions
  • CK (DDR)
  • WCK (DDR, QDR)
Supported Commands
  • Refresh all banks (REFab)
  • Activate (ACT)
  • Write without mask (WOM)
  • Write without mask with autoprecharge (WOMA)
  • Read (RD)
  • Read with autoprecharge (RDA)
  • Precharge all banks (PREab)
  • Precharge per bank (PREpb)
  • No operation (NOP)
Initialization Power-up sequence
Interface Trainings
  • Command address training
  • WCK2CK training
  • Read training
  • Write training
Mode Registers Supports register functionality
Command Address Bus Inversion (CABI) The number of CA lines driving a LOW level can be limited to 5 in 2 channel mode or 7 in PC mode for 8Gb, 12Gb, and 16Gb densities and limited to 6 in 2 channel mode or 8 in PC mode for 24Gb and 32Gb densities
Data Bus Inversion (DBI)
  • Data on the bus can be inverted during both read and write to save power
  • Data Bus Inversion the feature can be set through mode register
Device Density Supports a wide range of device densities from 2Gb to 32Gb
Latency Code Frequency Table Supports and checks all read and write latency requirements for a given frequency
Tccd+n Reads and Writes Supports all combinations of Reads merging and Writes merging placed Tccd+n apart