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This Cadence® Verification IP (VIP) supports the JEDEC® DDR5 SDRAM Registered DIMM Design Specification, DDR5 RDIMM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 RDIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR5 RDIMM is the next-generation DIMM specification with improvements in the areas of speed, configuration, reliability, and power saving. It supports speeds up to 4400 speed grade.

Specification Support

The Memory Model for DDR5 RDIMM is evolving and supports the proposals that are balloted at JEDEC. The latest specification ballots are available at http://www.jedec.org.

Protocol Features

The following table describes key features from the specification that are implemented in the Cadence VIP for DDR5 RDIMM.

Feature Name

DIMM Types


DIMM Configuration Support

  • Supports up to 2 ranks

  • Supports dual independent channels


32Gb, 64Gb, and 128Gb


3200, 3600, 4000, 4400, and 4800

ECC Checks Bits

Optional DRAM instantiation for checks bits

Core RCD Forwarding Logic

All DRAM commands

RCD Data Rate

Supports DDR, SDR1, and SDR2 modes


Optional support for checking even parity; in case of errors: Gate DRAM commands


DCS Training( DCSTM ), QCS Training ( QCSTM ), DCA Training (DCATM ), CA Pass-Through mode ( CAPTM ), BCS Training, BCOM Pass-Through Mode

Control Word

Output Delay Control Word for CS, RW04 Control Word, most of the control word definitions are now supported

DRAM Features

Refer to the DDR5 SDRAM product page


32GB and 256GB


Single and Dual


x4 and x8


3200, 3600, 4000, 4400, and 4800

I2C Interface

Supports I2C interface for RCD

Output Delay Modeling

Supports Output Delay Modeling for RCD

Bus Inversion

Supports RCD Bus Inversion

Inter Rank Odt

Supports Inter Rank Odt Checks

Self Refresh

Supports Self Refresh with and without Clock Stop for RCD

Control Word Read and Write

Supports front-door access of RCD Control Word Registers, both Read and Write operations can be performed to RCD control word registers

Transparent Mode

Supports Transparent mode

Address Mirroring

DDR5 SDRAM supports the MIR pin, Host is not required to do anything special for odd Rank for all types of DDR5 DIMMs

Data Buffer Interface

Date Buffer interface is now supported by DDR5RCD, refer to DDR5 LRDIMM page for more details

Transaction Level CallBack

Supports DIMM transaction-level CallBacks


The following features are not yet supported in the DDR5 RDIMM and UDIMM:

  • DQS and DQ mapping configuration

  • SOMA load

  • Save and restore

Key Verification Capabilities

  • Back-door access: RCD Control Word Registers, Model state

  • Ability to dynamically change timing parameters

  • DIMM-level Callbacks

  • Fly-by delay and bit/trace delay support using DRAM board delays

  • RCD transaction callbacks

    • For each command executed after command latency
    • For each command forwarded to A/B channels
    • On-model state change
    • On-parity error recovery state change
    • For each assertion
  • RCD memory callbacks

    • Control word writes
    • Mode state changes (model state register writes)
    • Parity error log writes to control words
  • Assertion with configurable message severity
  • Registers to indicate DRAM and RCD model states

  • SideBand interface (Byte Mode and Block Mode Read Write commands are supported)
  • Refer to DDR5 DRAM for more verification capabilities at the DRAM level