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This Cadence® Verification IP (VIP) supports the JEDEC® DDR5 SDRAM Registered DIMM Design Specification, DDR5 RDIMM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model VIP for DDR5 RDIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR5 RDIMM is the next-generation DIMM specification with improvements in the areas of speed, configuration, reliability, and power saving. It supports speeds up to 4400 speed grade.

Specification Support

The Memory Model for DDR5 RDIMM is evolving and supports the proposals that are balloted at JEDEC. The latest specification ballots are available at http://www.jedec.org.


VIPCAT 11.3.062

Rev 0.85 for RCD

VIPCAT 11.3.051

Standard is evolving


Key Features 

The following table describes key features from the specification that are implemented in the VIP.

Feature Name

DIMM Types


DIMM Configuration Support

  • Supports up to 2 ranks

  • Supports dual independent channels


32Gb, 64Gb, and 128Gb


3200, 3600, 4000, 4400, and 4800

ECC Checks Bits

Optional DRAM instantiation for checks bits

Core RCD Forwarding Logic

All DRAM commands

RCD Data Rate

Supports DDR, SDR1, and SDR2 modes


Optional support for checking even parity; in case of errors: Gate DRAM commands


QCSTM Training

Control Word

Output Delay Control Word for CS

DRAM Features

Refer to the DDR5 SDRAM product page


32GB and 256GB


Single and Dual


x4 and x8


3200, 3600, 4000, 4400, and 4800

I2C Interface

Supports I2C interface for RCD

Output Delay Modeling

Supports Output Delay Modeling for RCD


The following features are not yet supported in the DDR5 RDIMM and UDIMM:

  • Front-door access of RCD Control Word Register

  • DQS and DQ mapping configuration

  • Fly-by delays

  • Address mirroring

  • Weak drive

  • SOMA load

  • Save and restore

Key Verification Capabilities

  • Back-door access: RCD Control Word Registers, Model state

  • Ability to dynamically change timing parameters

  • Callbacks

  • RCD transaction callbacks

    • For each command executed after command latency
    • For each command forwarded to A/B channels
    • On-model state change
    • On-parity error recovery state change
    • For each assertion
  • RCD memory callbacksAssertion with configurable message severity

    • Control word writes
    • Mode state changes (model state register writes)
    • Parity error log writes to control words
  • Registers to indicate DRAM and RCD model states

  • Refer to DDR5 DRAM for more verification capabilities at the DRAM level