DDR5

This Cadence® Memory Model Verification IP (VIP) supports the JEDEC Memory Device DDR5 SDRAM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for DDR5 SDRAM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The DDR5 standard is the next generation of DRAM device memory standard with many improvements in performance, reliability, and power saving over the previous generation of DRAM devices (DDR4). DDR5 addresses industry demand with increased bandwidth, capacity, power-saving features, and with more reliability through CRC and ECC.

Specification

The Cadence VIP for DDR5 is based on the JEDEC JESD79-5 specification.

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description

General DDR Functionality and Timing Checks

  • Strength modeling
  • Debug ports
  • Packet tracker
  • Prechange, Precharge Same Bank, Precharge All Bank
  • Reset
  • Initialization
  • Mode Register Set, Mode Register Write, Mode Register Read (front door and back), MR Truth Tables and Timings
  • Command Truth Table
  • Burst Length, Type, Order
  • Precharge Command
  • Programmable Preamble, Postamble, Interamble
  • Interamble
  • Activate Command
  • Write Operation
  • Read Operation
  • Self-Refresh Operation (with and without clock stop)
  • Power Down Mode
  • Input Clock Frequency Change
  • Maximum Power Saving Mode (MPSM)
  • Refresh Operation
  • Temperature Sensor
  • Multi-Purpose Command (MPC)
  • Per Dram Addressability (PDA)
  • Read Training Pattern
  • Read Preamble Training Mode
  • CA Training Mode (CATM)
  • CS Training Mode (CSTM)
  • Write Leveling Training Mode
  • ZQ Calibration Commands
  • VrefCA Command
  • VrefCS Command
  • Post Package Repair (PPR)
  • DQS Interval Oscillator
  • tDQS2DQ Offset
  • 2N Mode
  • Write Pattern Command
  • ECS Modes
  • CRC
  • CA_ODT Strap Operation
  • Refresh Management (RFM)
  • On-Die Termination (ODT)
  • Timing Parameters by Speed Grades e.g., bus timings (setup, hold, pulse width checks)
  • Protocol checks including spacing checks associated with all commands
  • Speed bin checks
  • Write Data Mask
  • SOMA Load
  • All Burst Lengths including BL32
  • CAI, MIR, CA_ODT Pin Support
  • Refresh, Refresh Same Bank (RefSb), Normal/FGR modes, Temp Based Refresh Rate, SREntry/Exit, etc
  • twr timing changes
  • MPC commands, e.g., Enter/Exit training, ZQ, 1N/2N, DLLReset, tDLLK/tCCDL, PDAEnum, Set RTT, ApplyVrefCARtt, etc
  • Power Down related timing parameters (trefpden, tactpden, tprpden, tmpcpden, tmrwpden_clk, and tmrwpden_time)
  • hPPR
  • sPPR
  • Read DQS Offset
  • On-Board delays
  • Support of Board Delays for All the Pins
  • Monitor Mode Support
  • Mpc Command Manual ECS Mode
  • Support for Inter Rank ODT Checks
  • Support for Inter Rank Command Spacing Checks
  • Support for Temperature Based Self Refresh with Temperature Sensor
  • Support for Active Byte Lane Mask for X16 device
  • DDR5 timings rounding algorithm
Command Decoding
  • Single-cycle and two-cycle commands with support for both targeted and non-targeted commands
  • 1N/2N Mode Support
Data Width x4, x8, and x16
Density 8Gb, 16Gb, 24Gb, and 32Gb
Programmable Configurations
  • Too many to list, refer to "3.5 Mode Registers" as per the feature support list, e.g., Burst Length, CL/CWL, Burst Type, Write Data pattern, PDA, Pre/post-amble, MPSM, MPCs s.a. RefRate/tdllk/tccdl/dllreset, etc
  • Trainings: WrLvl, RdPre, CA/CS, Rd training Pattern, etc
Speed 3200, 3600, 4000, 4400, and 4800
Bank Groups
  • Supports 8 or 4 bank groups
  • Modeling the concept and the timing associated with back-to-back accesses to the same and difference bank group
Refresh Options Normal 1X Refresh Mode, Fine Granularity 2X Refresh Mode, 1X Refresh Rate, 2X Refresh Rate

Key Verification Capabilities

  • Backdoor access to mode registers and device memory
  • Ability to dynamically change timing parameters
  • Callbacks: Detailed stranded out assertions for JESD79-5-specified checks with assertion coverage tracking and configurable message severity
    • Memory callback notifications on memory read and write accesses (transaction callbacks at all commands and Data UI)
    • Transaction protocol callback notifications at command execution, data pass, and errors reporting—for connecting user testbench scoreboard and reference model; also has ability to modify some fields to cause error injection (not in Verilog)
    • Callback notifications on initialization, bank, model state changes, and on mode register changes; alternatively, the testbench can poll this information anytime
  • Registers to indicate the model state, bank state, initialization state, and mode register states
  • Initialization can be optionally skipped
  • Refresh can be optionally skipped
  • Operating temperature-based refresh rate checking
  • Programmed dllk, cwl, cl, ccdl, and ccdl_wr mode settings checked to allowed speed
  • Inter-rank command spacing checks when interconnect description given
  • UVM Configuration: Run-time part selection (e.g., random constrained part query on speed, width, or any setting), run-time dynamic configurations (configure the VIP agent through the UVM config class)
  • Generic interface: A single generic ddr5 SDRAM interface (containing the union of all signals at max widths) works with any DDR5 SDRAM part (any width, depth, etc)
  • Mode register set/get by field name SV back-door APIs 
  • Built-in functional coverage mapped to spec annotated vPlan (vManager/vPlanner visual coverage to spec): >1000 feature grouped assertions, all mode settings, all command and associated fields per truth table, command sequences, mode dependent sequences, part characteristics, states
  • Advance Refresh and Temperature sensor verification support options, refer to the Cadence Online Support article for details
  • VIP Portal Catalog Explorer provides list of supported standard interface features: https://vipportal.cadence.com/web/guest/catalog-explorer

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