This Cadence® Memory Model Verification IP (VIP) supports the JEDEC® Memory Device DDR5 SDRAM standard. It provides a highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for DDR5 SDRAM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The DDR5 standard is the next generation of DRAM device memory standard with many improvements in performance, reliability, and power saving over the previous generation of DRAM devices (DDR4). DDR5 addresses industry demand with increased bandwidth, capacity, power-saving features, and with more reliability through CRC and ECC.

Specification Support

The specification for DDR5 SDRAM is evolving. The Cadence DDR5 VIP is based on the following specification:

JEDEC Standard

VIPCAT 11.30.062

Revision 0.83

VIPCAT 11.30.059


Key Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name


General DDR Functionality and Timing Checks
  • Reset
  • Initialization
  • Mode Register Write
  • Mode Register Read
  • Prechange
  • Precharge Same Bank
  • Precharge All Bank
  • Activate
  • Read
  • Write
  • MPC
  • Write Data Pattern and Refresh command
  • Bus timing (setup, hold and pulse width checks)
  • Protocol checks associated with all these commands
  • On-die Termination (ODT)
  • Power Down Mode
  • Self Refresh Mode
  • Speed bin checks (Partial Support)
  • CS Training Mode
  • CA Training Mode
  • Write Leveling
  • DM and DBI
  • CRC
  • SOMA Load
  • BL32
  • CAI, MIR, CA_ODT Pin Support
  • Programmable Preamble, Postamble
  • Mode register updates per .76 spec
  • Refresh Same Bank (RefSb)
  • twr timing changes
  • MPC Set RTT and ApplyVrefCARtt commands 
  • Power Down related timing parameters (trefpden, tactpden, tprpden, tmpcpden, tmrwpden_clk, and tmrwpden_time) are now supported
  • VRefCA command
  • hPPR
  • sPPR
  • Read DQS Offset
  • VRefCA
  • Monitor Mode
  • On-Board delays
  • RFM
Latest Command Decoding
  • Single-cycle and two-cycle commands with support for both targeted and non-targeted commands
  • 1N/2N Mode Support
Data Width x4, x8, and x16
Density 8Gb, 16Gb, 24Gb, and 32Gb
Configurations CL, CWL, AL, Burst Type, Burst Length, and Write Data pattern
Speed 3200, 3600, 4000, 4400, and 4800
Bank Groups
  • Supports 8 or 4 bank groups
  • Modeling the concept and the timing associated with back-to-back accesses to the same and difference bank group
Refresh Options 1X refresh mode and 2X refresh mode
The following features are not yet supported in the VIP for DDR5:
  • ECC and its visibility and associated functionality

Key Verification Capabilities

  • Backdoor access to mode registers and device memory

  • Ability to dynamically change timing parameter

  • Callbacks: Detailed stranded out assertions for JESD79-4-specified checks with assertion coverage tracking and configurable message severityRegisters to indicate the model state, bank state and initialization state

    • Memory and transaction callbacks for reads and writes; transaction callbacks for all other commands

    • Transaction protocol callbacks during command execution, data pass, and errors reporting—for connecting user testbench scoreboard and reference model; also has ability to modify some fields to cause error injection (not in Verilog)

    • Similar callback notifications to testbench on initialization, bank, and model state changes, and as mode register changes; alternatively, the testbench can poll this information anytime

  • Initialization can be optionally skipped

  • Refresh can be optionally skipped

  • UVM Configuration: Users can configure the VIP agent using the UVM config class