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DDR4 LRDIMM

This Cadence® Memory Model Verification IP (VIP) supports the JEDE® DDR4 Unbuffered DIMM (UDIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM) design standards. It provides a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for DDR4 RDIMM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR4 DIMM is the next-generation DIMM specification with improvements in the areas of speed, configuration, reliability, and power saving. It supports speeds up to 3200 speed grade. With redefined Control Word Write, DRAM Mode register write interface, and with new control word settings like programmable latency and encoded quad modes, it is more flexible. Guarding of the command forwarded to DRAMs and the RCD Control word writes with optional parity checking and detailed specification for different ways of recovery in the case of parity errors makes this more reliable.

Specification Support

The Memory Model for DDR4 RDIMM supports the following standards:

Release
Standard
VIPCAT 11.3.058
  • DDR4 SDRAM UDIMM Design Specification Revision 1.00
  • DDR4 SDRAM RDIMM Design Specification Revision 1.00
  • DDR4 SDRAM Load-Reduced DIMM Design Specification Revision 1.00
  • DDR4RCD02 Revision 1.00
  • DDR4DB02 Revision 1.00
VIPCAT 11.3.031
  • DDR4 SDRAM UDIMM Design Specification Revision 1.00 DRAFT
  • DDR4 SDRAM RDIMM Design Specification Revision 1.00 DRAFT
  • DDR4 SDRAM Load-Reduced DIMM Design Specification Revision 1.00 DRAFT
  • DDR4RCD02 Revision 0.85 draft
  • DDR4DB02 Revision 0.85 draft

Product Highlights

  • Back door accesses: RCD Control Word Registers, Model state
  • Change timing parameters dynamically by the user
  • Callbacks
  • RCD transaction callbacks
  • For each cycle with the details of inputs being latched
  • For each command executed after command latency
  • For each command forwarded to A/B sides
  • For each command to forwarded to DB on BCOM
  • For feedback during CA training mode
  • On model state change
  • On parity error recovery state change
  • For each assertion
  • RCD memory callbacks
  • Control word writes
  • Mode state changes (model state register writes)
  • Parity error log writes to control words
  • DDR4 Data Buffer
  • The model supports following training modes:
    • DRAM Interface MDQ Receive Enable Phase (MREP) Training Mode
    • DRAM Interface Write Leveling (DWL) Training Mode
    • Host Interface Write Leveling (HWL) Mode
    • DRAM-to-DB Read Delay (MRD) Training Mode
    • DB-to-DRAM Write Delay (MWD) Training Mode
  • The training sequences are one of the first think controllers that will know what Buffer Control Word (BCW) to be sent to the Data Buffer, so that the Data Buffer can set the signal delays (both DQS and DQ) for reads and writes
  • The Data Buffer model has JEDEC specification-defined checks for various combination of Read and Write commands spacing between different Rank
  • The Data Buffer model supports important features such as Command Sequence Error checking and PDA and PBA modes
  • Detailed stranded out assertion with configurable message severity
  • Registers to indicate DRAM and RCD model states
  • Refer to DDR4 SDRAM for more verification capabilities at DRAM level

Key Features

Feature Name
Description
Weak Driver Support
Supports signal strength modeling, users can use pull up or pull down on the inout pins and the model detects the signal strength and function like a real device
DIMM Types
DDR4 UDIMM, RDIMM, LRDIMM, DDR4 3DS, 3DS UDIMM, 3DS RDIMM, and 3DS LRDIMM
New DIMM Configuration Support
Raw Cards with CB bits are mapped to the middle of DQ and DQS buses
Configurable DIMM Topology
A number of ranks and components with and the overall interconnect between DIMM, RCD and DRAM are configurable using SOMAs
Supports Flyby delay to specify wiring delays
  • For UDIMMs, Flyby delays can be specified from DIMM connectors to each of the DRAMs individually
  • For RDIMMs, Flyby delays can be specified from DIMM connectors to RCD for command and control pins, and from RCD Side A/B to each of the DRAMs individually
For LRDIMMs, Flyby delays can be specified from DIMM connectors to RCD for command and control pins, and from RCD Side A/B to each of the DRAMs individually
  • Additionally, the inout pins can specify the delay to and from DB to each DRAM inout ports
Flyby delays can be changed on the fly using mmsomaset
ECC Checks Bits
Optional DRAM instantiation for checks bits
Address Mirroring
RDIMM will optionally mirror the address bits as mentioned in specification
DQ Maps
Configurable DQ Maps to match one of the options mentioned in the specification
Initialization and Reset
Use Power Up Reset and Reset with Stable Power with all timing and pin validity checks
Core RCD Forwarding Logic
DRAM MRS command handling, inversion, mirroring, command latency, propagation delay, gating with parity checks, and different CS modes
RCD Control Word Writes
MRS7 interface for CWW and most of the control word settings
Parity
  • Supports optionally checking for even parity. CWW and DRAM commands support gating errors
  • Implements different recovery mechanisms defined in the specification
CA Training
Supports Clk to CA and ODT, CKE, CSBAR loop-back modes
DB Control Word Writes
MRS7 interface for Buffer Control Word Writes and most of the control word settings
DB Data Latching and Forwarding
Latching of Read and Write data to forward it to Host, or the DRAM side depending on the command
Supports all the Nibble and bit-lane delay registers mentioned in the specification
DB Command Sequence and Parity
Supports the command sequence and Parity error along with the relevant buffer Control Words
LRDIMM Training Modes
Fully supports DWL, HWL, MREP, MRD and MWD Training modes
LRDIMM Rank to Rank Timing Checks
Supports timing check for Read and Write accesses to different Ranks
DRAM Features
Refer to DDR4 SDRAM