DDR4

This Cadence® Memory Model Verification IP (VIP) supports the JEDEC Low Power Memory Device, DDR4 SDRAM standard. It provides a mature, highly capable compliance verification solution that supports simulation, and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for DDR4 SDRAM is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR4 standard is the next generation of DRAM device memory standard with many improvements in performance, reliability, and power saving over the previous generation of DRAM devices (DDR3). With datacenters, cloud computing, and number of cores in a system increasing every day, there is a demand for high capacity and more bandwidth. With the increase in the capacity and bandwidth percentage of power consumed by memories, power consumed by the whole system is also increasing and price, performance, and wattage is becoming more important as well. DDR4 addresses most of these issues with increased bandwidth, capacity, new power-saving features, and with more reliability through CRC and Parity. DDR4 is not backward compatible with DDR3.

Specification Support

The Memory Model for DDR4 SDRAM supports the officially released JESD79-4B specification and 3DS extensions. The specification is available at https://www.jedec.org/sites/default/files/docs/JESD79-4.pdf

Release

JEDEC Standard

VIPCAT 11.3.058

JESD79-4B

VIPCAT 11.3.031

JEDEC JC-42.3C

Product Highlights

  • Back Door Accesses: To More Registers, MPRs, and device memory as well

  • Ability to dynamically change timing parameter values or swap parts (SOMAs)

  • Callbacks:

    • Memory and transaction callbacks for reads and writes; transaction callbacks for all other commands

    • Transaction protocol callbacks at command execution, data passes, and errors for inclusion in the testbench scoreboard and reference model, with user ability to modify some fields for error injection (not in Verilog)

    • Similar callback notifications to the testbench on initialization, bank, model state changes as well as mode register changes; alternatively, the testbench can poll this information anytime

  • Detailed stranded out assertions for JESD79-4-specified checks with assertion coverage tracking and configurable message severity

  • Registers indicate the model state and initialization state

  • Protocol faults to model erroneous read DQs strobes

  • Controller randomizes read output delays

  • Optional skipping of initialization

  • Optional skipping of Refresh

  • Differential clock checks with configurable skew

  • UVM Configuration: Ability to configure the VIP agent using the UVM config class

Key Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name

Description

Parity Error Injection

Supports Parity Error injection using callbacks

3DS Level

Supports command decoding

3DS Read and Write

Supports 3DS Read and Write commands for 2H, 4H, and 8H combinations

General DDR Functionality and Timing Checks

Precharge, Activate, Read, Write, Mode Register Write, Write leveling, ODT checks, Power Down, Self Refresh, Initialization, and all related timing checks

Reduced Pin Count

A16..A14 are multiplexed with ras, cas and webar pins and dedicated act pin for Activate command

Data Width, Density

4, 8, and 16. 2 Gb to 16 Gb

Configurations

New mode registers and associated settings

Speed

1600, 1866, 2133, 2400, 2666, and 3200

Bank Groups

Modeling the concept and the timing associated with the back-to-back accesses to the same and difference bank group

More Read Training Options

More MPR registers organized as pages, more options of reading those registers and preamble training

Reading of Mode Register Settings

Some important setting of the more registers are shadowed into page-2 MPRs

Data Mask and Data Bus Inversion

Data on the bus can be inverted during both read and write to save power; both Data Mask and Data Bus inversion features can be set using mode registers

Per-DRAM Addressing

Allows mode registers of each DRAM on the DIMM to be programmed independently

CAL Mode

Allows CSBAR to be asserted a few cycles before actual command details

Write CRC

CRC is checked for writes and passes the error to the controller; CRC failures will let the write go through if Data Mask is disabled, and will block writes if that Mask is enabled

Parity

Parity checking is off by default, but when enabled parity is checked for each command before execution and also detailed recovery in case of errors and reporting of logs through MPR Reads

Control Gear Down Mode

Allows the DRAM to operate in 2N mode

New Read Output Delay

The tDQSCK jitters are defined in the specification and they drift per operating voltage and temperature; the VIP models this and allows the controller to configure the drift and skew

Configurable Preamble

Allows both 1CK and 2CK preambles to be selected for both read and writes

Refresh Options

Normal mode refresh, self refresh, temperature controller self refresh, Low Power Array self refresh, and fine-granularity refresh

Maximum Power Saving Mode

Preserves the mode register settings, but loses data

RTT

Complete modelling of all RTT values, RTT_NOM, RTT_Park, and RTT_Wr with the internal register representing the value of RTT at a given point of time, based on the mode of operation

Connectivity Test Mode

Allows DRAM to enter CT Mode when Test Enable (TEN) pin is asserted HIGH