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DDR PHY Interface (DFI) Monitor

The Cadence® DDR PHY Interface (DFI) Monitor Verification IP (VIP) is a mature and proven VIP solution, supporting all DFI protocols including the latest DFI 5.0. The product monitors transactions of DFI bus and reports errors if transactions violate any DFI protocol.

Specification Support

The Cadence DFI Monitor VIP supports the following specifications: 1.0, 2.0, 2.1, 2.1, 3.0, 3.1, 4.0, Addendum to DFI 3.1 Version 2, and DFI 5.0.

The DFI protocol specifications are developed and maintained by the DFI Group and are accessible to registered users at: http://www.ddr-phy.org


VIPCAT 11.30.055

  • DFI 5.0

VIPCAT 11.30.050

  • Preliminary DFI 4.0

  • Addendum to DFI 3.1

    January 30, 2015

VIPCAT 11.30.031

  • Preliminary DFI 4.0

  • Addendum to DFI 3.1

    April 2, 2014

VIPCAT 11.30.031

  • DFI 4.0

Key Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name


Default value check till dfi_init_complete is not asserted

Write Transactions

Transactions related to Write command

Read Transactions

Transactions related to Read command

PHY Update

MC and PHY initiated update process

Frequency Change

Frequency change protocol

Frequency Ratio Support

Allowing 1:2:4 frequency ratio between DFI and PHY clocks


Parity checking protocol

Read Leveling

Read Leveling and Gate Training transactions

Write Leveling

Write Leveling transactions

CA Training

CA Training support is available for DFI 3.1

Low Power Control

Handshaking enables PHY to enter low-power state. (Including DFI5.0 enhancement)

LP4 General Changes

General changes for I/O and control for LPDDR4 support

LPDDR4 Channel

Support of two DFI channel in combine/independent mode for LPDDR4

DB Training

Data Buffer training for DDR4 support

Per Slice Read Leveling

Support for independently per slice leveling

Read Data Eye Training Sequence Enhancement

Read Data Training Enhancement for LPDDR4 support

Read/Write Chip Select

_n removed from signals dfi_wrdata_cs_n and dfi_rddata_cs_n for DFI 4.0

Write Leveling Strobe Update

Write Leveling Strobe Update for LPDDR4 support

WR DQ Training

Write DQ Data Eye Training for LPDDR4 support

Frequency Indicator

Frequency Change protocol with new added signal

DFI Disconnect Protocol

Disconnect Procedure for Update and Training Interface

Data Bit Disable

Valid data bits for both the MC and PHY on both the dfi_wrdata and dfi_rddata interfaces

Slice Parameter

The width of a common PHY data slice Component

Gear Down Mode

Handshaking enables Gear Down Mode

3D Stack Support

3D Stack Support for DDR4

Update Interface Clarification on Self Refresh Exit

The behavior of the dfi_ctrlupd_req signal just after self-refresh exit

Inactive CS

States of chip select Active/Inactive

Remove DFI Training

Remove DFI Training signal from Interface

PHY Independent Training Boot Sequence

Support for PHY Independent Training Boot sequence

MC to PHY Communication Interface

Support for MC To PHY Communication Interface

LPDDR5 Frequency Change

Support for LPDDR5 Frequency Change

LPDDR5 WCK Control

Support for LPDDR5 WCK Control

Clock Domains

Support for Clock Domains for All Memories

2N Mode

Handshaking enables 2N Mode

DFI Interactions

Support for Interactions between the Update, Status, PHY Master and Low Power Interfaces

Clock Disable

Support Clock disabling feature

Key Verification Capabilities

The DFI monitor allows you to selectively enable and disable various protocol checks, allowing you to use the monitor while your MC or PHY model is still under development. The severity of error messages can be changed to Error, Warning, Info, or Silent. Key DFI protocol checks are listed below:

  • Check signals for invalid X values

  • Check for correct default values

  • Check update interface protocols

  • Check protocols for read, write, and gate leveling

  • CA leveling protocol

  • Check initialization protocol

  • Check read and write protocols: Low-power protocol check

    • Check data enable and data valid assert and reject errors

    • Command interrupted by other commands

  • Check PHY master interface protocol

  • LPDDR4 Two channel check

  • DB Training check

  • Per slice read leveling check

  • Read data eye training sequence enhancement check

  • Write DQ training check

  • Checks for Disconnect protocol

  • Checks for LPDDR5 WCK Control

  • Checks for MC to PHY Communication Interface