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VIP for DFI

VIP for DFIMC

The Cadence® Verification IP (VIP) for DDR PHY Interface Active Memory Controller (DFIMC) provides a mature, highly capable compliance verification solution for the DFIMC protocol. The VIP supports simulation platform and enables metric-driven verification of IP and system on chip (SoC) designs against DFI protocol specifications. The DFIMC VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators.

Specification Support

DDR_PHY_Interface_Specification_v4_0
DDR_PHY_Interface_Specification_v5_0

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description
Supported Memory

Command Interface

Drives Command on different phases based on memory protocol requirement

DDR5, LPDDR5, and LPDDR4

Data Interface

Read and Write Data Interface

DDR5, LPDDR5, and LPDDR4

Update Interface

MC-initiated and PHY initiated updates

DDR5, LPDDR5, and LPDDR4

Training Interface

CA, Write, Write DQ, Read Training (both MC initiated and PHY initiated)

LPDDR4

PHY Master Interface

Support for PHY Master Interface

DDR5, LPDDR5, and LPDDR4

WCK Interface

Support for WCK Interface

LPDDR5

Frequency Change Protocol

Initiates frequency change

DDR5, LPDDR5, and LPDDR4

Low Power Control

Initiates Low-Power Entry as per DFI5.0 and DFI4.0

DDR5, LPDDR5, and LPDDR4

Data CS Gap

Data Path Chip Select Gap (Per Rank Delay line support)

DDR5, LPDDR5, and LPDDR4

Refresh Command

Sends Refresh All and Refresh Per Bank command on every internal

 DDR5, LPDDR5, AND LPDDR4

Low Power Control

Handshaking enables PHY to enter low-power state. (Including DFI5.0 enhancement)

DDR5, LPDDR5, and LPDDR4

DFI Interactions

DFI Interaction rules as per DFI 5.0

DDR5 and LPDDR5

2N Mode

Command transmission in 2N Mode

DDR5

DBI and Data Mask

Generates Inverted/Masked Write Data and Invert received Read Data with dfi_rddata_dbi enabled

DDR5, LPDDR5, and LPDDR4

CRC

Generates CRC and Error injection

DDR5

Frequency Ratio

All possible frequency ratios as per specification

DDR5, LPDDR5, and LPDDR4

Key Verification Capabilities

  • SystemVerilog coverage infrastructure for extendable coverage

  • Callbacku-based error injection capability for creation of illegal stimulus from the VIP

  • Monitor agent with analysis ports, which can be used for score-boarding purpose

  • Transaction tracker: Configurable tracking of all the transactions on the channels

Known Limitations

  • Multi-Channel support for LPDDR4

Other Supported Features

Testbench Language Interfaces

SytemVerilog

UVM Methodology

Up to Version 1.2

Trace Debug

Yes

Functional Coverage -e

No

Functional Coverage -SV

Yes

Triple Check Yes

VIP for DFI Active PHY

For information on DFI Active PHY, please contact David Peña, Director of Product Strategy.

VIP for DFI Monitor

The Cadence®Verification IP (VIP) for DDR PHY Interface (DFI) Monitor is a mature and proven VIP solution, supporting all DFI protocols including the latest DFI 5.0. The product monitors transactions of DFI bus and reports errors if transactions violate any DFI protocol.

Specification Support

The Cadence DFI Monitor VIP supports the following specifications: 1.0, 2.0, 2.1, 2.1, 3.0, 3.1, 4.0, Addendum to DFI 3.1 Version 2, and DFI 5.0.The DFI protocol specifications are developed and maintained by the DFI Group and are accessible to registered users at: http://www.ddr-phy.org

Release
Standard

VIPCAT 11.30.055

  • DFI 5.0

VIPCAT 11.30.050

  • Preliminary DFI 4.0

  • Addendum to DFI 3.1

    January 30, 2015

VIPCAT 11.30.031

  • Preliminary DFI 4.0

  • Addendum to DFI 3.1

    April 2, 2014

VIPCAT 11.30.031

  • DFI 4.0

Key Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description

Initialization

Default value check till dfi_init_complete is not asserted

Write Transactions

Transactions related to Write command

Read Transactions

Transactions related to Read command

PHY Update

MC and PHY initiated update process

Frequency Change

Frequency change protocol

Frequency Ratio Support

Allowing 1:2:4 frequency ratio between DFI and PHY clocks

Parity

Parity checking protocol

Read Leveling

Read Leveling and Gate Training transactions

Write Leveling

Write Leveling transactions

CA Training

CA Training support is available for DFI 3.1

Low Power Control

Handshaking enables PHY to enter low-power state. (Including DFI5.0 enhancement)

LP4 General Changes

General changes for I/O and control for LPDDR4 support

LPDDR4 Channel

Support of two DFI channels in combine/independent mode for LPDDR4

DB Training

Data Buffer training for DDR4 support

Per Slice Read Leveling

Support for independent per slice leveling

Read Data Eye Training Sequence Enhancement

Read Data Training Enhancement for LPDDR4 support

Read/Write Chip Select

_n removed from signals dfi_wrdata_cs_n and dfi_rddata_cs_n for DFI 4.0

Write Leveling Strobe Update

Write Leveling Strobe Update for LPDDR4 support

WR DQ Training

Write DQ Data Eye Training for LPDDR4 support

Frequency Indicator

Frequency Change protocol with new added signal

DFI Disconnect Protocol

Disconnect Procedure for Update and Training Interface

Data Bit Disable

Valid data bits for both the MC and PHY on both the dfi_wrdata and dfi_rddata interfaces

Slice Parameter

The width of a common PHY data slice component

Gear Down Mode

Handshaking enables Gear Down Mode

3D Stack Support

3D Stack Support for DDR4

Update Interface Clarification on Self Refresh Exit

The behavior of the dfi_ctrlupd_req signal just after self-refresh exit

Inactive CS

States of chip select Active/Inactive

Remove DFI Training

Remove DFI Training signal from Interface

PHY Independent Training Boot Sequence

Support for PHY Independent Training Boot sequence

MC to PHY Communication Interface

Support for MC to PHY Communication Interface

LPDDR5 Frequency Change

Support for LPDDR5 Frequency Change

LPDDR5 WCK Control

Support for LPDDR5 WCK Control

Clock Domains

Support for Clock Domains for All Memories

2N Mode

Handshaking enables 2N Mode

DFI Interactions

Support for Interactions between the Update, Status, PHY Master and Low Power Interfaces

Clock Disable

Support Clock disabling feature

Key Verification Capabilities

The DFI monitor allows you to selectively enable and disable various protocol checks, allowing you to use the monitor while your MC or PHY model is still under development. The severity of error messages can be changed to Error, Warning, Info, or Silent. Key DFI protocol checks are listed below:

  • Check signals for invalid X values

  • Check for correct default values

  • Check update interface protocols

  • Check protocols for read, write, and gate leveling

  • CA leveling protocol

  • Check initialization protocol

  • Check read and write protocols: Low-power protocol check

    • Check data enable and data valid assert and reject errors

    • Command interrupted by other commands

  • Check PHY master interface protocol

  • LPDDR4 Two channel check

  • DB Training check

  • Per slice read leveling check

  • Read data eye training sequence enhancement check

  • Write DQ training check

  • Checks for Disconnect protocol

  • Checks for LPDDR5 WCK Control

  • Checks for MC to PHY Communication Interface