This Cadence® Verification IP (VIP) supports the JEDEC® Low-Power Memory Device, LPDDR5 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for LPDDR5 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The LPDDR5 standard is an industry-leading low-power volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The LPDDR5 Low-Power Memory Device Standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 4G networks.

Specification Support

The VIP for LPDDR5 Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.


JEDEC Standard

VIPCAT 11.30.063

JESD209-5, FEBRUARY 2019

Key Features  

Key features of the LPDDR5 device standard supported by the Cadence LPDDR5 VIP are listed below:

Feature Name

Bank Architecture

8B, 16B, and 4BankGroup supported.

General DDR Functionality

  • Command Decoding and related error conditions 
  • Activation, Precharge, and Mode Register Write and Read, CAS, Mask Write, Read, Write, Mask Write, Power Down, Refresh, Self Refresh, and DSM command and related timing checks
  • WCK2Ck synchronization
  • 4:1 and 2:1 WCK to CK ratio
  • Core timing
  • Initialization Sequence
  • Read FIFO and Write FIFO 
  • ZQ Calibration, Read DQ Calibration, and Write Leveling
  • Bus timing (setup, hold)
  • WCK off timing
  • WCK2DQ oscillator
  • ODT on timings
  • Enhanced RDQS training mode
  • WCK2DQ AC timings for low and high frequency
  • tDQSQ, tHZDQ, tCSLCK, tCKCSH, and tHZDQS timings
  • Clock frequency change and clock stop
  • RDQS timing support
  • RDQS toggle mode
  • FSP Specific Mode Register memories
  • VREF Current Generator (VRCG)
  • Differential Clock (CK, WCK) checks
  • Duty Cycle Monitor (DCM)
  • Temperature Derating support
  • Support for the timing parameters tWR2WCK, tMRW_PST, tDIPW, and tCIPW
  • Write clock-related timing parameters - tWCH, tWCL, tWCK(avg), and tJIT
  • Checkers for the conditions when Input Clock Stop and frequency change is not allowed
  • Updates as per latest ballots to WS_FS command
  • Rank-to-rank timing constraints update based on 1854.59 ballot
  • WXS, WXSA, and WXSB support (byte controllable writex)
  • NT-ODT-based rank-to-rank timing constraints update based on 1851.66B ballot
  • Core timing table when Link ECC is enabled
  • DMI Pin behavior with Write-related commands dependent on WECC(MR22) and Datacopy(MR21)
  • DMI Pin behavior with Read-related commands dependent on RECC(MR22) and Datacopy(MR21)
  • Link ECC WCK-RDQS_t/Parity Training using FIFO
  • Write and Read Link ECC
  • Read and Write Datacopy
  • Enhanced WCK always On
  • Support for tODTup, tDQ7FSP, and tWCKSUS timing parameters


800MHz (6400 Mbps)

Mode Registers

Supports register functionality

Configurable Preamble and Postamble

Allows preamble and postamble to be configured for Read, Write and Mask Write

Data Bus Inversion

Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register

Device Density

Supports a wide range of device densities from 2Gb to 32Gb

Frequency Set Points    

Allows LPDDR5 to be switched between two different operating frequencies by duplicating mode register parameters commonly changed with operating frequency

Exploration Mode

Model acts as a passive monitor in exploration mode. This means only command and clock needs to fed to the model and rest of pins such as WCK, RDQS, DQ, and DMI need not be connected. The model only checks for command protocol and does not drive data. There is no activity on the data bus but all other command spacing are supported. At present, Model is supporting exploration mode forRead, MRR, Write, and Mask Write commands.

Multipurpose Command (MPC)

Supports all 6 MPC commands

Command Bus Training    

The training centers the internal VREF(ca) in the CA data eye and, at the same time, allows for timing adjustments of the CS and CA signals to meet setup and hold requirements

Latency Code Frequency Table

Supports and checks all read and write latency requirements for a given frequency

Tccd+n Reads and Writes

Supports all combinations of Reads merging and Writes merging placed Tccd+n apart

Delay Modeling

Delay modeling of input and output signals, display of delay modeling internal signals on the simulator waveform

Single-Ended Clock

Single-Ended Clock, Write Clock, and RDQS support

Byte Mode (x8)

Support for Byte Mode devices


Support for refresh rates and options to control the application of new rates

Rank to Rank Timing Checks

Support for rank2rank timing checks using LPDDR5MDP (Multi Package DRAM)

Key Verification Capabilities

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory

  • Ability to dynamically change the timing parameter

  • Ability to check for errors and change error severity

  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)

  • Registers to indicate the model state, bank state, and initialization state

  • Initialization can be optionally skipped

  • UVM Configuration: Users can configure the VIP agent using the UVM config class

  • Functional coverage

  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker