LPDDR5

The LPDDR5 standard is an industry-leading low-power volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The LPDDR5 Low-Power Memory Device Standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 4G networks.

Specification Support

The VIP for LPDDR5 Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at http://www.jedec.org.

Release

JEDEC Standard

VIPCAT 11.3.051

Samsung LPDDR5 Specification Draft_R096

 

Early Adopter Program

The Early Adopter Program allows customers to gain early access to the Denali® Memory Model for LPDDR5, enabling the accelerated adoption of emerging memory protocols and, more importantly, to influence memory model product requirements to meet their project timelines by working closely with our architects and the broader Denali Memory Model team.  

For more information, please contact David Peña, Director of Product Strategy.

Product Highlights

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Ability to dynamically change the timing parameter
  • Ability to check for errors and change error severity
  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)
  • Registers to indicate the model state, bank state, and initialization state
  • Initialization can be optionally skipped
  • UVM Configuration: Users can configure the VIP agent using the UVM config class
  • Functional coverage

See the Verification IP Support Home for more information.

Key Features  

Key features of the LPDDR5 device standard supported by the Cadence LPDDR5 VIP are listed below:

Feature Name
Description
Bank Architecture
8B, 16B, and 4BankGroup supported.
General DDR Functionality
  • Command Decoding and related error conditions 
  • Activation, Precharge, and Mode Register Write and Read, CAS, Mask Write, Read, Write, Mask Write, Power Down, Refresh, Self Refresh, and DSM command and related timing checks
  • WCK2Ck Synchronization
  • 4:1 and 2:1 WCK to CK ratio
  • Core Timing
  • Initialization Sequence
  • Read FIFO and Write FIFO 
  • ZQ Calibration, Read DQ Calibration, and Write Leveling
  • Bus timing (setup, hold)
  • WCK off Timing
  • WCK2DQ oscillator
  • ODT on timings
  • Enhanced RDQS training mode
  • WCK2DQ AC timings for Low and High Frequency
  • tDQSQ, tHZDQ, tCSLCK, tCKCSH, and tHZDQS timings
  • Clock Frequency change and clock stop
  • RDQS timing support
  • RDQS toggle mode
Speed
800MHz (6400 Mbps)
Mode Registers
Supports register functionality.
Configurable Preamble and Postamble
Allows preamble and postamble to be configured for Read, Write and Mask Write
Data on the bus can be inverted during both read and write to save power. Data Bus Inversion the feature can be set through mode register.
Device Density
Supports a wide range of device densities from 2Gb to 32Gb.
Frequency Set Points    
Allows LPDDR5 to be switched between two different operating frequencies by duplicating mode register parameters commonly changed with operating frequency.
Exploration Mode
Model acts as a passive monitor in exploration mode. This means only command and clock needs to fed to the model and rest of pins such as WCK, RDQS, DQ, and DMI need not be connected. The model only checks for command protocol and does not drive data. There is no activity on the data bus but all other command spacing are supported. At present, Model is supporting exploration mode forRead, MRR, Write, and Mask Write commands.
Multipurpose Command (MPC)
Supports all 6 MPC commands.
Command Bus Training    
The training centers the internal VREF(ca) in the CA data eye and, at the same time, allows for timing adjustments of the CS and CA signals to meet setup and hold requirements.
Latency Code Frequency Table
Supports and checks all read and write latency requirements for a given frequency.
Tccd+n Reads and Writes
Supports all combinations of Reads merging and Writes merging placed Tccd+n apart.