This Cadence® Memory Model Verification IP (VIP) supports the JEDEC® Low Power Memory Device, LPDDR4 standard. It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for LPDDR4 is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

The LPDDR4 standard is an industry-leading low-power volatile (DRAM) device memory standard for storage of system code, software applications, and user data. LPDDR4 Low Power Memory Device Standard is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smart phones, tablets, ultra-thin notebooks, and similar connected devices on the newest, high-speed 4G networks.

The Cadence Memory Model for LPDDR4 supports JEDEC LPDDR4X standard. The LPDDR4X memory saves additional power by reducing the I/O voltage to 0.6V from 1.1V. Other LPDDR4X improvements include a single-channel die option for smaller applications, new MCP, PoP, and IoT packages, and additional definition and timing improvements.

Specification Support

 The Cadence LPDDR4 VIP is based on the following specification:

JEDEC Standard

VIPCAT 11.30.048


VIPCAT 11.30.040

  • Addendum No. 1 to JESD209-4, Low Power Double Data Rate 4X (LPDDR4X)
  • Latest LPDDR4 specification JESD209-4A is fully supported

VIPCAT 11.3.031


Product Highlights

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Comprehensive assertion library: Includes a large number of assertions for assertion coverage
  • Ability to check for errors and change error severity
  • Error injection during Write, Write FIFO, and CA Training
  • Fine-grained control for read and write DQS skew for both channels
  • Pseudo registers for model state, bank state, and initialization state, which can be read anytime though backdoor access to know the device state
  • Randomization of the read output delays
  • Transaction and memory callbacks for all protocol and device memory events (Read/Write)

See the Verification IP Support Home for more information.

Key Features

Key features of the LPDDR4 device standard supported by the Cadence VIP are listed below:

Feature Name
Dual Channels
Supports two channels that can function independently
General DDR Functionality and Timing Checks
Precharge, Activate, Read, Write, Mask Write, Mode Register Read, Mode Register Write, Power Down, Refresh, Self Refresh, and related timing checks
Device Density
Supports a wide range of device densities from 4Gb to 32Gb
Speed (Mt/s)
2133MHz (4266 MT/s)
Data Mask and Data Bus Inversion
Data on the bus can be inverted during both read and write to save power
Both Data Mask and Data Bus inversion features can be set through mode registers
On-the-Fly Burst Length
Bust length during Read, Write and Mask Write can be set on the fly through command data and mode registers
Configurable Preamble and Postamble
Allows preamble and postamble to be configured for Read, Write, and Mask Write
Frequency Set Points    
Allows LPDDR4 to be switched between two differing operating frequencies by duplicating mode register parameters commonly changed with operating frequency
FIFO Register and DQS-DQ Training
Supports Read FIFO and Write FIFO commands used during Write training
Multipurpose Command (MPC)
Supports all 7 MPC commands
Command Bus Training    
The training centers the internal VREF(ca) in the CA data eye and, at the same time, allows for timing adjustments of the CS and CA signals to meet setup and hold requirements
Latency Code Frequency Table
Supports and checks all read and write latency requirements for a given frequency
Vref Settings
Supports CA and DQ voltage reference settings
Single-Ended Mode 
Supports single-ended mode for Clock and Strobe
Supports byte-mode devices from 2Gb to 32Gb
Tccd+n Reads/Writes
Supports all combinations of Reads merging and Writes merging placed Tccd+n apart