HBM3

This Cadence® Verification IP (VIP) provides support for the High-Bandwidth Memory (HBM3). It provides a highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The Memory Model for HBM3 models a single channel of HBM3 DRAM; this model can be replicated for multiple channels and stacks. The Memory Model for HBM3 runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The HBM3 DRAM standard is an industry-leading, low-power, double-data-rate, high-data-width, volatile (DRAM) device memory standard for storage of system code, software applications, and user data. The HBM3 DRAM Memory Device Standard is designed to satisfy the performance and memory density demands of the leading-edge high-performance devices.

Protocol Features

The following table describes key features implemented in the Memory Model for HBM3.

Feature Name
Description

Signaling

Supports the following pins:

  • DQ[63:0]

  • C[7:0]

  • R[9:0]

  • 1 DBI/DM per 8 DQS

  • 1RDQS_t/RDQS_c, WDQS_c per 32 DQs

Clocking and Reset

Differential clock inputs (CK_t/CK_c) and Active Low Reset Line (reset_n)

Addressing

All addressing schemes with Pseudo Channels are supported 

Device density from 2Gb to 32Gb per channel is supported

Device configuration from 8Gb High to 32 Gb 16 High are supported

Row Command Decode

  • Row NO-OP

  • Activate

  • Precharge

  • Precharge All

  • Per Bank Refresh

  • All Bank Refresh

  • Per Bank Refresh Management

  • All Bank Refresh Management

  • Power Down Entry

  • Self Refresh Entry

  • Power Down / Self Refresh Exit

Column Command Decode

  • Column No-OP

  • Read

  • Read with Auto Precharge

  • Write

  • Write with Auto Precharge

  • Mode Register Set

  • Mode Register Read

Speed (MHz)

Clock: 1200MHz; data rate: 6.4 Gbps/pin

Mode Registers

Mode registers as per HBM2E specification are supported

General HBM3 Functionality and Timing Checks

Precharge, Activate, Read, Write, Mode Register Set, Power Down, Self Refresh, and all related timing checks

Activate/Precharge

Activate/Precharge functionality is supported

Read/Write

RDQS is used for Reads and WDQS for Writes; strobe frequency is the same as that of the main clock; auto-precharge feature is supported

SID

The stack ID (SID) acts as a bank address bit during command execution

Self Refresh

All timing checks associated with SR is implemented

Power Down

PD is supported with all timing checks

State Machine

Implements HBM3 state machine

Core Timing Parameters

Core timing parameter checks are included

Command Spacing

Command spacing checks

Bank Groups

Timing associated with back-to-back accesses to the same and different bank group

Exceptions – The following features are not supported:

  • WDQS is not used for Reads

  • Data Mask and Data Bus Inversion

  • Command, Data Parity

  • Initialization

  • Refresh checks and management

  • Lane Repair

  • Loopback Mode

  • IEEE 1500 Functionality

  • Memory array MBIST

  • INTEST TX and INTEST RX

  • ECC

Key Verification Capabilities

  • Backdoor access: Allows backdoor read and write to mode registers as well as device memory

  • Ability to dynamically change timing parameter values or swap parts (SOMAs)

  • Memory and transaction callbacks for commands, data, and events

  • Comprehensive assertion library: Includes a large number of assertions for assertion coverage

  • UVM configuration: The user can configure the VIP agent using the UVM config class

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory

  • Ability to check for errors and change error severity

  • Registers to indicate the current state of HBM state machine

  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker