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DDR5 LRDIMM

This Cadence® Verification IP (VIP) provides support for the JEDEC DDR5 SDRAM Unbuffered, Registered, and Load-Reduced DIMM Design Specification, DDR5 UDIMM/RDIMM/LRDIMM standard. It provides a mature, highly capable compliance verification solution that supports simulation and formal analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The DDR5 LRDIMM Memory Model VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

DDR5 LRDIMM is the next-generation DIMM specification with improvements in the areas of speed, configurability, reliability, and power saving. It supports speeds up to 4400 speed grade. With redefined Control Word Write, DRAM Mode register write interface, and with new control word settings like programmable latencies, encoded quad modes, it is more flexible. Guarding of the command forwarded to DRAMs and the RCD Control word writes with optional parity checking and detailed specification for different ways of recovery in the case of parity errors makes this more reliable. Additionally, the data bus latency can be programmed.

Specification Support

The DDR5 LRDIMM memory model is evolving and supports the proposals that are balloted at JEDEC and VIP supports:

  • JEDEC DDR5 SDRAM Design Specification(Rev 1.01)

  • JEDEC DDR5 Registering Clock Driver Design Specification DDR5RCD01 - Latest Revision

  • JEDEC DDR5DB01 for the Data Buffer - Latest Revision

Protocol Features 

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description

Weak Driver Support

Support for signal strength modeling, users can use pull up or pull down on the input pins and the model will be able to detect the signal strength and function like a real device

DIMM Types

DDR5 UDIMM, RDIMM, and LRDIMM

New DIMM Configuration Support

  • Supports up to 2 ranks

  • Supports dual independent channels

Configurable DIMM Topology

Number of ranks and components with and the overall interconnect between DIMM, RCD, and DRAM are configurable using SOMAs

Size

32Gb, 64Gb, and 128Gb

Speed

3200, 3600, 4000, 4400, and 4800

ECC Checks Bits

Optional DRAM instantiation for checks bits

Core RCD Forwarding Logic

All DRAM commands

RCD Data Rate

Supports DDR, SDR1, and SDR2 modes

Parity

Optional support for checking even parity; in case of errors: Gate DRAM commands

Training

QCSTM Training

Control Word

Output Delay Control Word for CS, RW04 Control Word

DRAM Features

Refer to the DDR5 SDRAM product page

Density

32GB and 256GB

Rank

Single and Dual

DRAMs

x4 and x8

Speed

3200, 3600, 4000, 4400, and 4800

I2C Interface (RCD)

Supports I2C interface

Output Delay Modeling (RCD)

Supports Output Delay Modeling

Bus Inversion (RCD)

Supports RCD Bus Inversion

Inter Rank Odt

Supports Inter Rank Odt Checks

Self Refresh (RCD)

Supports Self Refresh with and without Clock Stop

Transaction Level CallBack

Supports DIMM transaction-level callBacks

Independent Nibble Delays (DB)

Supports all the Lower and Upper Nibble Delay settings for each of the 2 supported ranks

Control Words (DB)

  • Directed and Paged Control Words

  • Rank Training Control Words

  • Periodic Update and Snoop Setting Control Words

  • Supports Read/Write(Command/Backdoor) of 100s of Control Words

Power Saving Modes (DB)

  • Power Down With/Without ODT

  • Self Refresh With/Without Clock Stop

BCOM Training (DB)

Supports all the BCOM Training Modes

1N/2N Command Modes (DB)

Supports both 1N/2N Command Modes

Initialization (DB)

  • Power on initialization

  • Reset with stable power with and without clock stop

Command Support (DB)

Supports all of BCOM commands

Training Modes Support (DB)

  • Transparent Mode

  • DQ Pass Through Mode

Per Buffer Addressability (PBA) Mode (DB)

PBA Mode similar to PDA in DRAM

Strobe/Data Training Support (DB)

  • MRE: DRAM Interface MDQS Receive Enable Training Mode
  • MRD: MDQS Read Delay Training Mode
  • MWD: DB-to-DRAM Write Delay Training Mode
  • DWL: DRAM Write Leveling Training Mode
  • HWL: Host Interface Write Leveling Training Mode
  • HIR: Host Interface Read Training Mode
  • HPA: Host Preamble Training Mode

Extensive Protocol and Timing Checks (DB)

Exceptions

The following features are not yet supported in the DDR5 RDIMM/LRDIMM:

  • DQS and DQ mapping configuration

  • Fly-by delays

  • SOMA load

  • Save and restore

  • DDR5DB: Continuous Burst Mode, ODT, Dual Frequency, and Loopback Mode support

  • DIMM-level wrapper with RCD/SDRAM and DB Models instantiated inside, example template for SV wrapper is available

Key Verification Capabilities

  • Back door accesses: RCD Control Word Registers, DB Control Word Registers, Model state

  • Change timing parameters dynamically by the user

  • Each component-level Callbacks

  • DDR5 RCD

    • Transaction callbacks

      • For each command executed after command latency

      • For each command forwarded to A/B channels

      • On-model state change

      • On-parity error recovery state change

      • For each assertion

    • Memory callbacks

      • Control word writes

      • Mode state changes (model state register writes)

      • Parity error log writes to control words

  • DDR5 Data Buffer

    • Transaction callbacks

      • For each command executed after command latency

      • On-model state change

      • For each assertion

    • Memory callbacks

      • Control word writes

      • Mode state changes (model state register writes)

  • Detailed stranded out assertion with configurable message severity

  • Registers to indicate DRAM, RCD, and DB model states

  • SideBand Interface (Byte Mode and Block Mode Read Write commands are supported)

  • Refer to DDR5 DRAM for more verification capabilities at DRAM level

Other Supported Features

Methodologies Unified Verification Methodology (UVM), OVM
Simulators IES, VCS, and MTI
Testbench Language Interfaces Verilog, VHDL, SystemVerilog, e, and SystemC®
Trace Debug Yes

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