xSPI JESD251xSPI JESD251xSPI JESD251

xSPI

The Cadence® Memory Model Verification IP (VIP) for xSPI provides verification of xSPI (Extensible SPI) NOR flash devices using the SPI protocol. The xSPI VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.  

Specification Support

The VIP for xSPI Memory Model is evolving and supports most of the proposals that are balloted at JEDEC. The latest ballots/specifications are available at www.jedec.org.

The xSPI VIP complies with the following JEDEC Standards and Vendors:

Release
JEDEC Standard
Starting the VIPCAT 11.30.064 update build of August, 2019
  • JEDEC Standard JESDS251 Profile 1 Version 1.0 July 2018
  • JEDEC Standard JESD251-A1 Revision October 2018
  • JESD Standard JESD252 Revision 2018
  • JEDEC Standard JESD216D Revision November 2018 
  • ADESTO: SFDP (Serial Flash Discovery Parameter) Table, 1 May 2018 

Key Features

The following table describes key features from the specification that are implemented in the xSPI VIP for Profile 1.

Feature Name
Description

Read SFDP Command

SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes

Modes Switching Commands

Command to enter OCTAL(E8h), QPI(38h), and SPI(FFh) modes

SCCR (Status Control and Command Register)

Write status control register command (71h)

Register Fields: STR_DTR, WEL, OME, Variable Dummy Cycle, and QPIE (14th DWORD)

Volatile and Non-Volatile offset address

Register Bits: EPE, Erase Error, Program Error, DPDS, WIP

Read status register

Read Command

SPI (Read Zero Latency), Quad (As per JESD251-A1), and Octal modes

Data Rate: STR and DTR

Supports SPI, DUAL (1-1-2,1-2-2), QUAD, and OCTAL modes

Read Fast Wrapped and Set up Read Wrapped

Addressing Capability

3-byte and 4-byte address modes

Enter and Exit 4-byte mode

Program Operation

Byte and Page Program

Data Rate: STR and DTR

Supports SPI, Quad, and OCTAL modes

Program Suspend and Resume command

Ease Operation

Chip Erase and Block Erase (4, 32, 64, and 256KB) command

Erase Suspend and Resume command

Deep Power Down

 Deep Power Down feature

Soft Reset Feature

Soft reset with reset enable (0x66) and reset command (0x99) with return to default protocol mode

Command Extension Feature

Command Extension Feature for Octal DTR mode (8D-8D-8D)

Shared Pin Feature

Shared IO3 Pin with Hold Pin and Shared IO3 Pin with Reset Pin

Note:

1. With an xSPI license you can use features of both xSPI and OSPI VIPs.

2. SFDP Headers, Parameter Headers, Parameter DWORDS for above commands are supported.

3. xSPI VIP supports JESD251 Profile 1. Profile 2 is not supported yet.

Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity

  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory

  • Ability to dynamically change the timing parameter

  • Ability to check for errors and change error severity

  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)

  • UVM Configuration: Users can configure the VIP agent using the UVM config class