The Cadence® Memory Model Verification IP (VIP) for xSPI provides verification of xSPI (Expanded SPI) NOR flash devices using the SPI protocol. The VIP for xSPI is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

Specification Support

The VIP for xSPI is compliant to the following latest JEDEC specifications and Memory Vendors:

  • JEDEC standard JESD251 Profile 1 Version 1.0 July 2018: Expanded Serial Peripheral Interface (xSPI) for nonvolatile memory devices 
  • JEDEC Standard JESD251-A1 Released in October 2018: A1 - Amendment is for x4 Quad IO with Data Strobe 
  • JESD standard JESD252 Released in October 2018: Serial Flash - Reset Signaling protocol
  • JEDEC Standard JESD216D Revision November 2018: Serial Flash Discoverable Parameters 
  • ADESTO: DS_XP032_114G_122018
  • MICRON: tn1235_sfdp_mt35x Rev. B 10/18 EN (TN-12-35 SFDP for MT35X Family)
    Note: Micron is compliant to JESD216B ONLY.

  • MACRONIX: P/N: AN0726, REV. 1, October 08, 2019 for Part MX66UM2G45G
  • CYPRESS: Document Number: 002-18216, Rev *M Revised February 04, 2019

Protocol Features

The following table describes key features from the specification that are implemented in the xSPI VIP for Profile 1.

Feature Name
Supported Modes
  • Full SPI and O-SPI modes of Profile 1
  • Q-SPI: SFDC Read, Page Read, Page Program, Block Ease, Status Register write and read commands as per JESD251-A1
Read SFDP Command

SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes

Modes Switching Commands Command to enter OCTAL(E8h), QPI(38h), and SPI(FFh) modes
SCCR (Status Control and Command Register)
  • Write status control register command (71h)
  • Register Fields: STR_DTR, WEL, OME, Variable Dummy Cycle, and QPIE (14th DWORD)
  • Volatile and Nonvolatile offset address
  • Register Bits: EPE, Erase Error, Program Error, DPDS, WIP
  • Read status register
Read Command
  • SPI (Read Zero Latency), Quad (As per JESD251-A1), and Octal modes
  • Data Rate: STR and DTR
  • Supports SPI, DUAL (1-1-2, 1-2-2), QUAD, and OCTAL modes
  • Read Fast Wrapped and Set up Read Wrapped
Addressing Capability
  • 3-byte and 4-byte address modes
  • Enter and Exit 4-byte mode
Program Operation
  • Byte and Page Program 
  • Data Rate: STR and DTR
  • Supports SPI, QUAD, and OCTAL modes
  • Program Suspend and Resume command
Erase Operation
  • Chip Erase and Block Erase (4, 32, 64, and 256 KB) command
  • Erase Suspend and Resume command
Deep Power Down Deep Power Down feature
Soft Reset Feature Soft reset with reset enable (0x66) and reset command (0x99) with return to default protocol mode
Command Extension Feature Command Extension Feature for Octal DTR mode (8D-8D-8D)
Shared Pin Feature Shared IO3 Pin with Hold Pin and Shared IO3 Pin with Reset Pin
Command Support sFDP Headers, Parameter Headers, and Parameter DWORDS for above commands
  1. xSPI includes both VIP for xSPI and VIP for OSPI NOR.
  2. xSPI JESD251 Profile 2 is not supported.
  3. For complete vendor-specific Quad-SPI functionalities in addition to Q-SPI defined in JESD251-A1, user will require VIP for Q-SPI.

Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity
  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Ability to dynamically change the timing parameter
  • Ability to check for errors and change error severity
  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)
  • UVM Configuration: Users can configure the VIP agent using the UVM config class
  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker