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This Cadence® Verification IP (VIP) upgrades the SD CARD and SDIO verification platform with Ultra High Speed Type II (UHS-II) support defined in the UHS-II Addendum specification of Part 1 Physical Layer Specification Version 4.00. It allows seamless verification of legacy SD CARD and SDIO protocol (version 3.00 and below) and the latest UHS-II interface. The UHS-II interface allows access to traditional SD CARD and SDIO applications through the SD-TRAN layer and to the UHS-II memory space through the CM-TRAN layer. The VIP allows full-stack UHS-II interface verification (TRAN + LINK + PHY) through the serial interface (D0, D1 and RCLK) and protocol IP verification (stripped of PHY) through PHY-LINK I/F defined in the specification.

Specification Support

The relevant specifications are Part 1 Physical Layer Specification Version 4.00 and Part 1 UHS-II Addendum Version 1.00. Both are available on request from SD Association's Members Site: https://www.sdcard.org/home/

Protocol Features

Important supported features are listed in the table below.

Feature Name

2L-HD Mode        

Half-duplex mode of operation that doubles data throughput 


Interface defined in Appendix-F allows verification of protocol IP independently

Data Burst Streaming

Allows multiple model instances to be connected using ring connection

Data Burst Retry

Data Burst Retry support through the simulation of recoverable error

Boot Code Loading

Boot code can be loaded from one of the model instances designated as boot device

Low Power Mode

Low Power Mode supported through configuration register setting

Speed Range A and B

Default Speed Range A and faster Range B supported through configuration register setting

Exceptions: The model currently does not support additional lanes (beyond D0 and D1) defined in the specification required for 2D1U-FD mode, 1D2U-FD mode, and 2D2U-FD mode.

Key Verification Capabilities

  • Callback events for packets at entry/exit of LINK layer and Transaction layer on the receive and transmit sides

  • Error injection in transmitted packets, either through predefined, available abstract error types or by directly modifying packet contents

  • Callback events at PHY layer to monitor bus activity and to inject errors

  • Configuration through SOMA or configuration register writes in CONFIG state or through back-door access into configuration register space


Example test cases in SystemVerilog or with UVM are available on request. See the Verification IP Support Home for more information.