Home: IP Portfolio > Verification IP > Memory Models > Q-SPI (Quad SPI )

Q-SPI (Quad SPI )

The Cadence® Verification IP (VIP) for Quad SPI (Q-SPI) provides verification of Q-SPI NOR devices using the SPI protocol. The VIP for Q-SPI is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

Specification Support

The VIP for Q-SPI supports features of vendors such as GigaDevices, Macronix, Winbond, Cypress, and Micron. The specification is available from the vendors.

Protocol Features

Key features of the Q-SPI device standard supported by the Cadence VIP are listed below:

Feature Name

Operation Mode

Supports Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI) with single and double transfer rate (STR and DTR)

Device Density

Supports a wide range of device densities from 256Mb to 2Gb

Frequency Support

Supports frequency up to 166MHz

Reset Functionality

Soft reset using the Reset command and Hard reset using the Reset Pin are available

Page Read

Supports READ, FAST READ, 2READ, DREAD, 4READ, QREAD instructions in STR and DTR mode

Page Program

Supports PAGE Program, Dual Page Program, and Quad Page Program instructions in STR and DTR mode

Addressing Capability

The 3-byte and 4-byte address modes enable memory access beyond 128Mb

Configuration Capability

Volatile and non-volatile configuration register settings to change the mode of the model, dummy cycle number forFASTread operation, and 3-byte or 4-byte addressing

Preamble Data Pattern

Based on the PBE (Preamble Bit Enable) bit value, Selected Preamble Pattern will be inputted to the Dummy Cycles

Erase Capability

  • Bulk erase (Chip Erase )

  • Sector erase uniform granularity

  • Sub-sector erase 4KB, 32KB, 64KB granularity

Security and Write Protection

ONe-time program (OTP) array of 1024 bytes

Status Register bits to control protection against program or erase of a contiguous range of sectors

  • Hardware and software control options

  • Advanced Sector Protection (ASP)

  • Individual sector protection controlled by boot code or password

Block Protection: (BP[3:0] and TB ) define protected area size

Burst Read

By using Set Burst Length command user can set 16-byte, 32-byte, and 64-byte Wrap Bursts for Read commands

Fast Boost Feature

The Fast Boot feature will provide the ability to automatically execute Read operation after Power on cycle or Reset without any Read command based on the configuration of Fast Boot register values

Deep Power Down

Supports Deep Power Down Mode and does not accept commands except Release and Exit from the Deep Power Down Command

Device and Feature Indentification

Electronic signature

  • JEDEC-standard 3-byte signature

  • Extended device ID: two additional bytes identify

Device factory options

Additional Functionalities

  • Execute-in-place (XIP)

  • PROGRAM and ERASE SUSPEND operations

  • Read Q-SPI Discoverable parameter (ReadSFDPcommand)

  • Data Learning Registers

  • High-performance Read mode


Supports Device Input and Output timing and Variants memory operations timing (such as Program, Erase, Suspend, and Resume)

Configuration Registers

1. Volatile Configuration Register 1

2. Non-Volatile Configuration Register 1

3. Volatile Configuration Register 2

4. Non-Volital Configuration Register 2

Quad-SPI Commands

Quad Input Output command quadruple the transfer bandwidth for READ and PROGRAM commands. Quad SPI Mode uses DQ [3:0].

Supported READ Commands Supported PROGRAM Commands
  • Quad Output Fast Read

  • Quad I/O Fast Read

  • DTR Quad Output Fast Read

  •  DTR Quad I/O Fast Read

  • 4-Byte Quad Output Fast Read

  • 4-Byte Quad I/O Fast Read

  • DTR 4-Byte Quad Fast Read

  • DTR 4-Byte Quad I/O Fast Read

  • Quad Input Fast Program

  • Extended Quad Input  Fast Program

  • 4-Byte Extended Quad Input Fast Program

  • 4-Byte Extended Quad Input Fast Program

  • DTR 4-Byte Quad Input Fast Program




Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity

  • Allows back-door Reads and Writes to volatile and non-volatile registers (Configuration and Security) as well as device memory

  • Ability to dynamically change the timing parameter

  • UVM Configuration: Ability to configure the VIP agent using the UVM config class