The Cadence® Memory Model Verification IP (VIP) for Flash Octal SPI (OSPI) Flash provides verification of serial flash NOR devices using the SPI protocol. The OSPI VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

Specification Support

The model supports Octal SPI features of the following vendors: Micron, Macronix, and Adesto. The specification is available from the respective vendors. 

  • Micron: Rev. E 12/16 EN
  • Macronix: REV. 1.2, December 08, 2016, MX25LW51245G-Automotive Revision May 2018
  • Adesto: ATXP032 DS-XP032–114E–11/2017

Product Highlights

  • Transaction callback events on requests and responses to monitor activity
  • Backdoor Reads and Writes to volatile and non-volatile registers (configuration and security) as well as device memory
  • Error injection support for ECC
  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker

Key Features

The following table describes key features from the specification that are implemented in the VIP:

Feature Name


Operation Mode

Supports Extended SPI mode as well as Octal SDR and DDR mode (Single I/O and Octal I/O)

Device Density

Supports a wide range of device densities from 256Mb to 2Gb

Frequency Support

Supports Frequency up to 133MHz in Single I/O mode and 200MHz in Octal I/O mode

Reset Functionality

Soft Reset (using the Reset command) as well as Hard Reset (using the Reset Pin)

Page Read (Micron)

Read (SPI mode only), Fast Read, Octal Output Read, Octal I/O Fast Read, DDR Octal Output Fast read, and DDR Octal I/O Fat Read (DDR mode only)

Page Read (Macronix)

Normal Read and Fast Read commands in SPI mode as well as Octal SPI mode

Page Program (Micron)

Page Program, Octal Input Fast Program, and Extended Octal Input Fast Program in Extended SPI and Octal DDR mode

Page Read (Macronix)

Page Program in SPI as well as DDR mode

Addressing Capability

3-byte and 4-byte address modes enable memory access beyond 128Mb

Configuration Capability

Volatile and non-volatile configuration register settings to change the mode of the model, Dummy cycles for read commands, 3-byte or 4-byte addressing, Output Drive Strength (ODS), DQS Enable and Disable, ECC enable and disable, CRC enable and disable, Wrap enable and disable, and Wrap size

Preamble Data Pattern (PBE)

Based on the PBE bit value, selected Preamble Pattern will be inputted to the Dummy Cycles

Erase Capability

  • Bulk erase (Chip Erase)

  • Sector erase uniform granularity

  • Sub-sector erase 4KB, 32KB granularity (for Micron)

Security and Write Protection

Volatile and nonvolatile locking and softwareWrite protection for each 128KB sector

  • Non-volatile configuration locking

  • Password protection

  • Protection Management Register offering enhanced

  • Security features

  • Hardware write protection: non-volatile bits

(BP[3:0] and TB) define protected area size

  • Program and erase protection during power-up

  • CRC detects accidental changes to raw data

Burst Read

By using Set Burst Length command you can set 16-byte, 32-byte, or 64-byte Wrap Bursts for Read commands

Fast Boot Feature

The Fast Boot feature provides the ability to automatically execute Read operation after Power on cycle or Reset without any Read command based on the configuration of Fast Boot register values

Deep Power Down

Model will support Deep Power Down Mode and will not accept any command in the Deep Power Down Mode except Release and Exit from From Deep Power Down Command

OTP Functionality (Macronix)

Additional 8K-bit Security OTP memory outside of storage memory

OTP Functionality (Micron)

Dedicated 64-byte OTP area outside main memory

  • Readable and user-lockable

  • Permanent lock with PROGRAM OTP command

Device and Feature Identification

Electronic signature

  • JEDEC-standard 3-byte signature

  • Extended device ID: two additional bytes identify

Device factory options

Additional Functionalities

  • Execute-in-place (XIP)

  • PROGRAM and ERASE SUSPEND operations

  • Read Serial Flash Discoverable parameter (Read SFDP command)

  • Software Reset commands (RESET and RESETEN)

  • Hardware Reset


Supports Device Input and Output timing and Variants memory operations timing (for Program, Erase, Suspend, and Resume)

Adesto Features

  • All features, commands, and timing parameters for SPI (1-1-1), QPI (4-4-4), and Octal (8-8-8) are supported in the model

  • Buffer Write (84h)

  • Buffer Read (D4h)

  • Buffer to Main Memory Page Program without Built-In Erase

  • WP pin functionalities (signals are shared with I/O pins)

  • Echo (AAh)

  • Echo with Inversion (A5h)

Read While Write (RWW - Macronix)

  • Divides into 2 banks of 0-32Mbit each

  • While an Erase or Program operation is taking place in one bank, a Read operation can take place in the other

  • Divides into 4 banks of 0-32Mbit each

DDR Center Aligned Read Strobe (DCARS - Macronix)

  • DQs is driven on 90-degree phase-shifted clock (sclk2) rather than actual clock (sclk)

Interruptible Write Buffer Sequence (Macronix)

  • Write Buffer Initial (WRBI)

  • Write Buffer Continue (WRCT)

  • Write Buffer Confirm (WRCF)

  • Page Buffer Read (RDBUF)