SPI NAND

The Cadence® Memory Model VIP for Flash SPI NAND provides verification of Flash NAND devices using the SPI protocol. The SPI NAND VIP supports SPI Nand features of the following vendors:

  • Giga
  • Macronix
  • Micron

The specification is available from the vendors.

Product Highlights

  • Transaction callback events on requests and responses to monitor activity
  • Backdoor access: Allows backdoor Reads and Writes to Mode registers as well as device memory
  • Ability to dynamically change the timing parameter
  • Ability to check for errors and change error severity
  • Transaction and memory callbacks for all protocol and device memory events (Read and Write)
  • Registers to indicate the model state, bank state, and initialization state
  • Initialization can be optionally skipped
  • UVM Configuration: Users can configure the VIP agent using the UVM config class

Key Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description
Set Features 0x1F, alter the device behavior of the device by writing device registers (Block Protection, Lock, OTP and Configuration, and Die select)
Get Features 0x0F, monitor the device status by reading device registers (Block Protection and Lock, OTP and Configuration, Status, Die select)
Read ID 0x9F, read the identifier code (Manufacturer ID and device ID) of the memory device
Page Read (to Cache) 0x13, transfers the data from the specified page of specified block of the memory device to the cache register (Buffer)
Read from Cache 0x03, 0x0B (Single I/O and SPI), read out the data from cache register (Buffer)
Read Page Cache Random (Micron) 0x30, 0xBB (Dual IO), 0xEB (Quad I/O, Q-SPI, and QSPI), read page(s) from specified block in sequential order or random order
Block Erase 0xD8, erase specified one block
Reset 0xFF, 0xFE, put the memory device into a known condition and to abort the command sequence in progress
Program Load 0x02, first reset the cache register to an all 0xFF value and then write the data into cache register (Buffer)
Program Execute 0x10, transfer of data from the cache register to the specified page of specified block of the memory device
Program Load Random Data 0x84, 0x34, 0xC4, programs or replaces data in a page with existing data (without resetting cache register)
Permanent Block Lock Protection (Micron) 0x2C, can lock 48 blocks per die permanently
HOLD# and WP# Pins HOLD Pin and Write Protected Pin functionalities
Operation Mode Supports Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI)

Quad SPI Support

Quad Input and Output commands quadruple the transfer bandwidth for READ and PROGRAM commands. Quad SPI Mode uses DQ [3:0].

Supported Read Commands
Supported PROGRAM Commands
Read from Cache Quad IO
Read from Cache x4
Program Load x4
Program Load Random Data x4