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The Cadence® Memory Model Verification IP (VIP) for HyperFlash provides verification of HyperFlash Controller using the Hyperbus protocol.

Specification Support

The model supports HyperFlash features of Cypress. The specification is available from the vendor.

  • Document Number: 001-99198 Rev. *H Revised February 06, 2017.

Protocol Features

The following table describes key features from the specifications that are implemented in the VIP.

Feature Name


Read memory array data

Word Program

Program data into memory

Write to Buffer

Program data to flash to memory

Device Density

Supports a device densities from 128Mb to 512Mb

Reset Functionality

Supports Reset functionality through:

Reset Output Pin Functionality

Supports RSTO# output to generate system level power-on reset

Interrupt (INT#) Pin Functionality

Supports INT# output to generate external interrupt during:

  • Busy to Ready Transition

  • ECC detection

DDR Center Aligned Read Strobe Functionality (DCARS)

Supports phase shifting of the RWDS signal with respect to the read data outputs using Phase Shifted Clock input PSC and PSC# pins

Configurable Burst Characteristics

Supports three kinds of bursts:

  • Wrapped burst

  • Supports Burst lengths: 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks)

  • Linear burst

  • Hybrid burst

    • One wrapped burst followed by linear burst

Also supports wrapped or linear burst type selected in each transaction

Status Register Read and Clear

Supports Read (0x70) and Clear (0x71) commands for Status Register

Power-on-Timer Register Program and Read

Supports Program (0x34) and Read (0x3C) commands for POR Timer Register

Interrupt Configuration Register Load and Read

Supports Load (0x36) and Read (0xC4) commands for ICR

Interrupt Status Register Load and Read

Supports Load (0x37) and Read (0xC5) commands for ISR

Volatile Configuration Register Load and Read

Supports Load (0x38) and Read (0xC7) commands for VCR

Non-Volatile Configuration Register Program, Erase and Read

Supports Program (0x39), Erase (0xC8) and Read (0xC6) commands for NVCR

Erase Commands

Supports the following Erase commands:

  • Chip Erase command (0x10)

  • Sector Erase command (0x30)

  • Evaluate Erase Status (0xD0)

Suspend and Resume Capability

Supports the following Suspend and Resume commands:

  • Erase Suspend command (0xB0)

  • Erase Resume command (0x30)

  • Program Suspend command (0x51)

  • Program Resume command (0x50)

Blank Check Command

0x33 confirms if the selected Flash Memory Array sector is fully erased or not

Enter Deep Power-Down

0xB9 supports Deep Power Down (DPD) entry command sequence to enter the DPD mode when the device is in the Standby state and not in an ASO

Program Buffer to Flash (Confirm)

0x29 transfers data from buffer to Flash Memory Array

Command Set Exit (0x90) Capability

Command Set Exit and ASPR ASO Exit (0x90) command for various ASOs, such as:


  • Password ASO


  • PPB Lock Bit ASO


Reset and ASO Exit (0xF0) Capability

Reset and ASO Exit (0xF0) command for various ASOs, such as:




  • Password ASO


  • PPB Lock Bit ASO


ID-CFI (Autoselect) ASO Capability

  • ID (Autoselect) Entry (0x90)

  • CFI Enter (0x98)

  • ID-CFI Read

  • ID-CFI ASO specific Reset and ASO Exit (0xFF)

 SSR (Secure Silicon Region) ASO Capability

  • SSR Entry (0x88)

  • Read

  • Word Program

  • Write to buffer

  • Program buffer to flash (confirm) (0x29)

  • SSR Exit

ASPR (ASP Configuration Register) ASO

  • ASP Register Entry

  • Program

  • ASPR Read

Password ASO Capability

  • Password ASO Entry (0x60)

  • Program

  • Read

  • Unlock (0x29)

PPB (Non-volatile Sector Protection) ASO Capability

  • PPB Entry (0xC0)

  • PPB Program (0x00)

  • All PPB Erase (0x30)

  • PPB Read

  • SA Protection Status (0x60)

PPB Lock Bit ASO Capability

  • PPB Lock Entry (0x50)

  • PPB Lock Bit Clear (0x00)

  • PPB Lock Status Read

 DYB (Volatile Sector Protection) ASO Capability

  • DYB ASO Entry (0xE0)

  • DYB Set

  • DYB Clear

  • DYB Status Read

  • SA Protection Status (0x60)

ECC Status ASO Capability

  • ECC Status Enter (0x75)

  • ECC Status Read

  • Error Lower Address Register (0xXX1)

  • Error Upper Address Register (0xXX2)

  • Read Error Detection Counter (0xXX3)

  • Clear ECC Errors (0x50)

CRC ASO Capability

  • CRC ASO Entry (0x78)

  • Load CRC Start Address (0xC3)

  • Load CRC End Address (start calculation) (0x3C)

  • CRC Suspend (0xC0)

  • Array Read (During Suspend)

  • CRC Resume (0xC1)

  • Read Check-Value Low Result Register (0xXX0)

  • Read Check-Value High Result Register (0xXX1)


Support Device Input and Output timing and Variants memory operations timing

Product Highlights

  • Transaction callback events are available on requests and responses to monitor activity

  • Allows backdoor Reads and Writes to volatile and non-volatile registers as well as device memory