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Flash ONFi

The Cadence® Memory Model Verification IP (VIP) for Flash ONFI is the verification solution for NAND flash memory interface based on any version of the Open NAND Flash interface. The VIP supports all the interfaces—SDR, NV-DDR, NV-DDR2, and NV-DDR3—as defined in the standard. The interface mode can be dynamically switched from one to another during the simulation. Through the "Volume Address" feature, defined in the latest standard, any number of device models can be connected to a single "chip enable" signal to allow testing of CE_n pin reduction scenarios.

Specification Support

All versions — 1.0, 2.0, 3.0, 4.0, 4.1, 4.2, and latest 5.0 ONFI — of the Open NAND Flash Interface available at http://www.onfi.org/specifications are supported.

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description

ZQ Calibration

New commands added in 4.0

Write DQ Training TX Side Write DQ Training at TX side commands 63h and 64h
Write DQ Training RX side Write DQ Training at TX side commands 63h and 64h
Timing Modes  Up to Timing Mode15 for ONFI4.2
SDR, NV-DDR, NV-DDR2 All three interfaces currently defined in the ONFI specification with ability to switch among interface modes dynamically
Reset

Reset the NAND Flash Device

Read Status and Read LUN Status Read the status of NAND device
Read ID Read Device Identification parameters
Read DQ Training Read DQ training command 62h
NV-DDR3 Available on low-voltage operation of the device and provides faster throughput
Multi-Plane Cache Operations Multi-Plane Cache Read and Program operations
Multi-Plane and Interleaved Operations Multi-plane Read, Program, Erase, and Copyback operations
Multi-LUN Operations Simultaneous Read/Program/Erase operations can be performed on multiple LUNs
Maximum Speed (NV-DDR3) 800MHz, 1600MT/s (DDR)
LUN Get/Set New feature commands added in 3.2
DCC Training Explicit (using Set Feature) and Implicit (18h) DCC Training
DBI Pin Features (ONFI5 Feature) Data Bus Inversion Pin and associated functionality as per JEDEC Committee - JC42.4 22 July 2020 as part of ONFI5.0
CE_n Pin Reduction

Allows multiple devices (model instances) to be connected to a single "chip enable"

Note: The matrix termination of ODT will not take effect even though ODT configure command is supported. However, self-termination only ODT can be activated through the “Set Feature” command. The non-ONFi commands (for example, vendor defined commands) are not supported.

Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity
  • Error injection capability through user modification of transaction contents
  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker