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Flash ONFi

The Cadence® Memory Model Verification IP (VIP) for Flash ONFi is the verification solution for NAND flash memory interface based on any version of the Open NAND Flash interface. The VIP supports all the interfaces—SDR, NV-DDR, NV-DDR2, and NV-DDR3—as defined in the fourth generation of the standard. The interface mode can be dynamically switched from one to another during the simulation. Through the "Volume Address" feature, defined in the latest standard, any number of device models can be connected to a single "chip enable" signal to allow testing of CE_n pin reduction scenarios.

Specification Support

All versions — 1.0, 2.0, 3.0, 4.0, 4.1, and 4.2 — of the Open NAND Flash Interface available at http://www.onfi.org/specifications are supported, the latest being 4.2.

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

Feature Name

ZQ Calibration

New commands added in 4.0

LUN Get/Set

New feature commands added in 3.2


Available on low-voltage operation of the device and provides faster throughput

CE_n Pin Reduction

Allows multiple devices (model instances) to be connected to a single "chip enable"


All three interfaces currently defined in the ONFi specification and switching among interface modes dynamically through "Set Feature" command

Multi-Plane and Interleaved Operations

Multi-Plane Read, Program, Erase, and Copyback operations

Multi-Plane Cache Operations

Multi-Plane Cache Read and Program operations

Multi-LUN Operations

Simultaneous Read/Program/Erase operations can be performed on multiple LUNs

Read ID

Read Device Identification parameters


Reset the NAND Flash Device

Related topic: Bypassing ONFI Reset Requirement

Read Status and Read LUN Status

Read the status of NAND device

DCC Training

Explicit (using Set Feature) and Implicit (18h) DCC Training

Read DQ Training

Read DQ training command 62h

Write DQ Training TX Side

Write DQ Training at TX side commands 63h and 64h

Write DQ Training RX side

Write DQ Training at TX side commands 63h and 64h

Timing Modes

Up to Timing Mode 15 for ONFI4.2

Maximum Speed (NV-DDR3)

800MHz, 1600MT/s (DDR)

Note: The matrix termination of ODT will not take effect even though ODT configure command is supported. However, self-termination only ODT can be activated through the “Set Feature” command. The non-ONFi commands (for example, vendor defined commands) are not supported.

Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity
  • Error injection capability through user modification of transaction contents
  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker

Examples and Usage Information

Example test cases in SystemVerilog or with UVM are available on request. See the Verification IP Support Home for more information.