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Flash Toggle NAND

Description

This Cadence® Verification IP (VIP) supports the Toggle NAND 1.0 and above specification. It is applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification to provide verification of Flash NAND devices using toggle mode DDR 2.0 and above. The VIP for Toggle NAND is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model. 

Supported specification: 

The VIP supports toggle NAND DDR 2.0 Single-Level-Cell (SLC) and Multi-Level-Cell (MLC) devices as well as Toggle NAND DDR 3.0/4.0 Single-Level-Cell (SLC), Multi-Level-Cell, and Triple-Level-Cell (TLC) devices from Hynix, Samsung, Toshiba, and SanDisk. The specification is available from the respective vendors. 

 

 

Product Highlights

  • Hundreds of protocol and timing checkers to easily catch design bugs
  • Hundreds of predefined configurations based on specific memory vendors part numbers datasheets or generic JEDEC definitions available on ememory.com  
  • Transaction and memory callbacks for all protocol, model states, and device memory events
  • Error injection capability through user modification of transaction contents (Below Version 2.0)
  • Packet tracker creation for easy debugging (Below Version 2.0)
  • Support testbench language interfaces for SystemVerilog, UVM
  • Ability to dynamically change configuration parameters

Key Features

The following table describes key features from the specification that are implemented in the VIP:

Feature Name
Description
Bits per Cell
  • Single-Level-Cell (SLC – 1-bit per cell) and Multi-Level-Cell (MLC – 2-bits per cell) devices support
  • SLC, MLC and Triple-Level-Cell (TLC – 3-bits per cell) devices support (Version 3.0/4.0)
Commands
  • Software Reset
  • Read ID
  • Read Status
  • Read LUN status
  • ODT turn on and off
Configurability
  • Page size in number of bytes
  • Number of pages per block
  • Number of blocks per Plane/LUN (die/stack)
  • Number of Planes/LUNs per target
  • Number of targets per device

LUN Features

Supports LUN Set and Get Features to set NAND device in certain modes

Memory Sizes 64Gb, 128Gb, 256Gb, and 512Gb
Multiple Die

Supports Multiple Die with shared Chip Select signal

Operations
  • Multi-Plane and Interleaved operations for Read, Cache Read, Program, and Erase Operation.
  • Multi-LUN Operations for simultaneous Read, Program, and Erase operations. 
Signals

Differential signals support for Data Strobe Signal and Read Enable Signal

Speed
  • Up to 200MHz or 400Mbps per DQ pin
  • Up to 600MHz or 1200Mbps per DQ pin (Version 3.0/4.0)

 

Simulation Testsuite 

Toggle NAND MM comes along with a set of example test scenarios for easy MM integration and evaluation

Testsuite link: "Please contact us for further information" 

 

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