This Cadence® Verification IP (VIP) supports the eMMC JEDEC standard. It is applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The eMMC VIP is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.

The eMMC standard is an industry-leading memory standard for embedded non-volatile storage of system code, software applications and user data. The new eMMC 5.1 JEDEC standard defines functionality that focuses on improving the interaction between the host processor and the memory device at the interface, configuration and protocol levels, resulting in potential gains in overall system performance and reliability.


Supports the JEDEC specifications:

  • JEDEC eMMC Electrical Standard, Version 4.51 (JESD84-B451)
  • JEDEC eMMC Electrical Standard, Version 5.0 (JESD84-B50)
  • JEDEC eMMC Electrical Standard, Version 5.1 (JESD84-B51)

Protocol Features

The following table describes key features from the specification that are implemented in the VIP.

General Model Features

Common queuing

Enhanced strobe in HS400 mode

Cache barrier

CID/CSD/OCR/Ext_CSD registers

Implements register bit definitions for a subset of eMMC standard bit definitions

High-Capacity Negotiation

For devices larger than 2GB, the addressing mechanism is switched from byte addressing to sector addressing

Initialization Checks

Checks for proper initialization sequence, this check can be skipped

Supports eMMC Command and Response Protocol

Implements 48-bit input command format and R1, R1b, R2, etc. response formats

State Machine and Timing Checks

Implements internal eMMC state machine and performs specified timing checks

Voltage Range Checking

As part of the CMD1 operation, the model will implement voltage range negotiation

eMMC 5.0/5.1 Features


Background Operation Control

Cache Command

Implements Cache Read/Write operations

Context IDs

Implements the Context Management functionality

Data Tag Mechanism

Implements Data tag mechanism

DDR Timing

Supports Dual Data Rate timing mode for Read/Write operations, reading CID and CSD registers, sending CRC status and Boot acknowledge

Discard Command

Implements Discard operation

Extended Partition Types

Implements Extended Partition Types operation

High-Speed 200MHz Mode

Implements 200 MB/s Read and Write operation


Supports High Priority Interrupt mechanism

Large(4Kb) Sector Size

Implements Read and Write operations for large 4Kb sector sizes

Packed Commands

Implements Packed Read and Write operation

Power Off Notification

Supports notification mechanism when the host intends to power off the device

Real Time Clock

Supports accepting Real Time Clock Information the host sends to the card


Implements Replay Protected Memory Block functionality

Sanitize Command

Implements Sanitize operation

High-Speed 400

Implements HS400 Dual Data Rate Read and Write interface

Data Strobe

Added a new signal "Data Strobe" which directs bit transfer on data lines in HS400 mode

Command Queuing

Added support for the command queuing feature


Key Verification Capabilities

  • Backdoor access: Allows backdoor writes to registers to enable error injection (status register) and dynamic configuration (Ext_CSD register)
  • Callbacks enable monitor implementation, protocol checks, and coverage collection
  • Comprehensive assertion library: Includes a large number of assertions for assertion coverage
  • Error injection capability via error control registers and SOMA settings
  • Traffic: Responds to bus traffic as a slave

See the Verification IP Support Home for more information.