Home: IP Portfolio > Verification IP > Memory Models > SDIO and SDCARD

SDIO and SDCARD

This Cadence® Memory Model Verification IP (VIP) supports the SD Memory Card that is specifically designed to meet the security, capacity, performance, and environment requirements inherent in newly emerging audio and video consumer electronic devices. The SD Memory Card includes a content protection mechanism that complies with the security of the SDMI standard and will be faster and capable of higher memory capacity.

In addition to the SD Memory Card, there is the SD I/O (SDIO) Card. The SDIO card is based on and compatible with the SD Memory card. This compatibility includes mechanical, electrical, power, signaling, and software. The intent of the SD I/O card is to provide high-speed data I/O with low power consumption for mobile electronic devices. The SDIO card may contain memory storage capability as well as its I/O functionality.

This verification IP product is available as part of the Memory Model Portfolio.

Specification Support

The relevant specifications are listed below.

SDIO and SDCARD  

They are available on request from SD Association's member site: https://www.sdcard.org/home/

  • SD Part 1 Version 4.2 (SDCARD)
  • SD Part E1 Version 4.00 (SDIO)
  • Part 1 Physical Layer Specification Version 3.01 
  • Part E1 SDIO Specification Version 3.00

SD Card 4.0

The relevant specifications are Part 1 Physical Layer Specification Version 4.00 and Part 1 UHS-II Addendum Version 1.00. Both are available on request from SD Association's Members Site: https://www.sdcard.org

Product Highlights

  • Callback events for packets at entry/exit of LINK layer and Transaction layer on the receive and transmit sides

  • Error injection in transmitted packets, either through predefined, available abstract error types or by directly modifying packet contents
  • Callback events at PHY layer to monitor bus activity and to inject errors
  • Configuration through SOMA or configuration register writes in CONFIG state or through backdoor access into configuration register space

Key Features

Important features are listed in the table below.

SDIO and SDCARD

Feature Name
Description

Capacity of Memory            

  • Standard Capacity SD Memory Card (SDSC): Up to and including 2 GB
  • High Capacity SD Memory Card (SDHC): More than 2GB and up to and including 32GB
  • Extended Capacity SD Memory Card (SDXC): More than 32GB and up to and including 2TB

Bus Speed Modes (4 data lines)

  • Default Speed mode: 3.3V signaling, frequency up to 25 MHz, up to 12.5 MB/sec
  • High Speed mode: 3.3V signaling, frequency up to 50 MHz, up to 25 MB/sec
  • SDR12: 1.8V signaling, frequency up to 25 MHz, up to 12.5MB/sec
  • SDR25: 1.8V signaling, frequency up to 50 MHz, up to 25MB/sec
  • SDR50: 1.8V signaling, frequency up to 100 MHz, up to 50MB/sec
  • SDR104: 1.8V signaling, frequency up to 208 MHz, up to 104MB/sec
  • DDR50: 1.8V signaling, frequency up to 50 MHz, sampled on both clock edges, 50MB/sec

Content Protection Mechanism

  • Content protection mechanism complies with highest security of SDMI standard
  • Password protection of card content

Write Protect Features

Built-in write protection features (permanent and temporary) and mechanical switch

Card Detection

Detecting insertion/removal of the card                   

Erase Mechanism

Erasing many write blocks simultaneously in order to enhance the data throughput

Function Extension

Support for function extension specification (Physical Layer Specification 4.1)

Event Indication Method

Support for FX_EVENT (Bit 6 of Card Status) (Physical Layer Specification 4.2)

SD Card 4.0

Feature Name
Description

2L-HD Mode

Half-duplex mode of operation, which doubles data throughput

Boot Code Loading

Boot Code can be loaded from one of the model instances designated as boot device

Data Burst Retry

Data Burst Retry support through the simulation of Recoverable error

Data Burst Streaming

Allows multiple model instances to be connected using Ring Connection

Low Power Mode

Low Power Mode supported through configuration register setting

PHY-LINK I/F

Interface defined in Appendix-F allows verification of Protocol IP independently

Speed Range A and B

Default Speed Range A and faster Range B supported through configuration register setting