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Memory Model VIP for HyperRAM

The Cadence® Memory Model Verification IP (VIP) for HyperRAM provides verification of HyperRAM controller using the HyperRAM protocol.

Specification Support

The model supports features of Cypress. The specification is available from the vendor. 

JEDEC Standard
VIPCAT 11.30.052 No standard.

Product Highlights

The following table describes key features from the specification that are implemented in the Memory Model VIP for HyperRAM.

Feature Name


Memory Read

Memory Read with Linear, Wrapped, and Hybrid Burst

Device Density

Supports device densities from 64Mb to 128Mb
Reset Functionality

Supports Reset functionality through:

  • Hardware Reset (via RESET# pin)
DDR Center-Aligned Read Strobe Functionality (DCARS)

Supports phase shifting of the RWDS signal with respect to the read data outputs using Phase Shifted Clock input PSC/PSC# pins

Configurable Burst Characteristics

Supports three kinds of bursts:

  • Wrapped burst
    • Supports Burst lengths: 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks), and 128 bytes (64 clocks)
  • Linear burst
  • Hybrid burst
    • One wrapped burst followed by linear burst

Also supports Wrapped or linear burst type selected in each transaction

Register Read

 Supports Read operation for following Registers:

  • Identification Register 0 (ID0)
  • Identification Register 1 (ID1)
  • Configuration Register 0 (CR0)
  • Configuration Register 1 (CR1)
Timing Support Device Input/Output timing and Variants memory operations timing

Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity
  • Backdoor access: Allows backdoor Reads and Writes to Volatile/Nonvolatile registers as well as device memory

Other Supported Features


Unified Verification Methodology (UVM), OVM
Testbench Language Interfaces Verilog, SystemVerilog
Trace Debug Yes

Interconnect Validator


Simulators IES, VCS, and MTI