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Memory Model for SPI NAND

The Cadence® Memory Model VIP for Flash SPI Nand provides verification of Flash NAND devices using the SPI protocol. 

Specification Support

The Memory Model VIP supports SPI Nand features of the following vendors:  Giga, Macronix, and Micron. The specification is available from respective vendors. 

Release
JEDEC Standard
VIPCAT 11.30.048 No standard.

Feature Highlights

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description
Set Features 0x1F, alter the device behavior of the device by writing device registers (Block Protection/Lock, OTP/Configuration, Die select)
Get Features 0x0F, monitor the device status by reading device registers (Block Protection/Lock, OTP/Configuration, Status, Die select)
Read ID 0x9F, read the identifier code (Manufacturer ID and device ID) of the memory device
Page Read (to Cache) 0x13, transfers the data from the specified page of specified block of the memory device to the cache register (Buffer)
Read from Cache 0x03, 0x0B, read out the data from cache register (Buffer)
Read Page Cache Random (Micron) 0x30, 0xBB, 0xEB, read page(s) from specified block in sequential order or random order
Block Erase 0xD8, erase specified one block
Reset 0xFF, 0xFE, put the memory device into a known condition and to abort the command sequence in progress
Program Load 0x02, first reset the cache register to an all 0xFF value and then write the data into cache register (Buffer)
Program Execute 0x10, transfer of data from the cache register to the specified page of specified block of the memory device
Program Load Random Data 0x84, 0x34, 0xC4, programs or replaces data in a page with existing data (without resetting cache register)
Permanent Block Lock Protection (Micron) 0x2C, can lock 48 blocks per die permanently
HOLD# and WP# Pins HOLD Pin and Write Protected Pin functionalities

Key Verification Capabilities

  • Transaction callback events on requests and responses to monitor activity

Other Supported Features

Methodologies

Unified Verification Methodology (UVM), OVM
Testbench Language Interfaces Verilog, SystemVerilog
Trace Debug Yes

Interconnect Validator

Yes