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Memory Model for OctaRAM

The Cadence® Memory Model VIP for OctaRAM provides verification of OctaRam/PSRAM controller using the Octram Double Data Rate RAM/PSRAM protocol. 

Specification Support

The model supports features of the following vendors: Macronix and Micron. The specification is available from respective vendors. 

Release
JEDEC Standard
VIPCAT 11.3.047 No standard.

Feature Highlights

The following table describes key features from the specification that are implemented in the VIP.

Feature Name
Description
Memory Read Memory Read with Continuous and Wrapped Burst
Sync Read Memory Read with Wrapped and Hybrid Burst
Memory Write Memory Write with Continuous and Wrapper Burst
Sync Write Memory Write with Wrapped and Hybrid Burst
Register Read Identification and Configuration Register Read
Register Write Configuration Register Write
Mode Register Read Mode Register Read for PSRRAM
Mode Register Write Mode Register Write for PSRAM
Preamble Bit Pattern Read Read Preamble Bit Pattern
64B Hybrid Wrap Read Read 64 Byte Hybrid Wrapped Data for PSRAM
64B Hybrid Wrap Write Write 64 Byte Hybrid Wrapped Data for PSRAM
Global Reset Reset PSRAM Device
Hardware Reset Hardware Reset Through RESETn Pin
Half Sleep Mode To Put PSRAM Device In Low Power State

Key Verification Capabilities

Transaction callback events on requests and responses to monitor activity

Other Supported Features

Methodologies

Unified Verification Methodology (UVM), OVM
Testbench Language Interfaces Verilog, SystemVerilog
Trace Debug Yes

Interconnect Validator

Yes