OctaRAM

The Cadence® Memory Model VIP for OctaRAM provides verification of OctaRam and PSRAM controller using the OctaRAM Double Data Rate RAM and PSRAM protocol. 

Specification Support

The model supports features of the following vendors: Macronix, Micron, and APMemory. The specification is available from respective vendors. 

Note: Micron uses the term PSRAM instead of OctaRAM.

Key Features

The following table describes key features from the specifications that are implemented in the VIP.

Feature Name
Description

Memory Read

Memory Read with Continuous and Wrapped Burst

Sync Read

Memory Read with Wrapped and Hybrid Burst

Memory Write

Memory Write with Continuous and Wrapper Burst

Sync Write

Memory Write with Wrapped and Hybrid Burst

Register Read

Identification and Configuration Register Read

Register Write

Configuration Register Write

Mode Register Read

Mode Register Read for PSRRAM

Mode Register Write

Mode Register Write for PSRAM

Preamble Bit Pattern Read

Read Preamble Bit Pattern

64B Hybrid Wrap Read

Read 64-byte Hybrid Wrapped Data for PSRAM

64B Hybrid Wrap Write

Write 64-byte Hybrid Wrapped Data for PSRAM

Global Reset

Reset PSRAM Device

Hardware Reset

Hardware Reset Through RESETn Pin

Half Sleep Mode

PSRAM Device In Low Power State

Read

16Mb and 64Mb Read in SPI mode without Wrapped Burst

Fast Read

16Mb and 64Mb Fast Read in SPI and QSPI mode without Wrapped Burst

Fast Read Quad

16Mb and 64Mb Fast Read Quad in SPI and QSPI mode without Wrapped Burst

Write

16Mb and 64Mb Write in SPI and QSPI mode without Wrapped Burst

Quad Write

16Mb and 64Mb Quad Write in SPI and QSPI mode without Wrapped Burst

Wrapped Read

16Mb Wrapped Read in SPI and QSPI mode with Wrapped Burst

Wrapped Write

16Mb Wrapped Write in SPI and QSPI mode with Wrapped Burst

Mode Register Read

16Mb Mode Register Read in SPI and QSPI mode

Mode Register Write

16Mb Mode Register Write in SPI and QSPI mode

Enter Quad Mode

Switch mode of operation from SPI to QSPI for 16Mb and 64Mb Memory

Exit Quad Mode

Switch mode of operation from QSPI to SPI for 16Mb and 64Mb Memory

Reset

16Mb and 64Mb Register Reset Sequence (Reset Enable: Enables Reset Operation + Reset: Resets the Register Space) in SPI and QSPI mode

 

Reset Enable

Burst Length Toggle

Switch the Wrapped Length to 32 byte from any value set in Mode Register 0 in SPI and QSPI mode for 16Mb Memory

Half Sleep Entry

Switch device in an ultra-low power state in SPI and QSPI mode for 64Mb Memory

Read ID

16Mb and 64Mb Read ID in SPI mode

Deep Power Down Mode and Enhancements for Memory size 128Mb

Key Verification Capabilities

  • Transaction callback events are available on request and responses to monitor activity
  • Packet Tracker support to debug transactions; for more information, see Working with VIP Packet Tracker